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DM9000A

APPLICATION NOTES

Preliminary 37
Version: DM9000A-AN-V121
November 27, 2007

6.4 IP/TCP/UDP checksums Offload

The DM9000A chip supports the IP/TCP/UDP checksum generations and status checking.

And enable the IP/TCP/UDP checksums offload function in the TCP/IP upper layers of the

embedded OS, while setting the DM9000A IP/TCP/UDP checksum generations and checking.

List powerful function bits in TCSCR & RCSCSR:

TX Check Sum Control Register (TCSCR REG. 31H):

Bit Name Description

UDPCSE UDP Check Sum Generation Enable

TCPCSE TCP Check Sum Generation Enable

IPCSE

IP Check Sum Generation Enable

RX Check Sum Control Status Register (RCSCSR REG. 32H):

Bit Name Description

UDPS

UDP Check Sum Status

0: checksum OK, if UDP packet received.

TCPS

TCP Check Sum Status

0: checksum OK, if TCP packet received.

IPS

IP Check Sum Status

0: checksum OK, if IP packet received.

UDPP

UDP Packet if indicating 1

TCPP

TCP Packet if indicating 1

IPP

IP Packet if indicating 1

RCSEN

Receive Check Sum Enable Checking

When set, the checksum status will be stored in packet first byte of status header.

DCSE

Discard Check Sum Error Packets

When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.

For example,

#define TCSCR

0x31

#define RCSCSR 0x32

iow ( TCSCR , 0x07 );

/* TX IPCSE + UDPCSE cs-generation enable */

iow ( RCSCSR , 0x03 );

/* RX checksums checking bad-pkt-discard enable */

/* IPS/TCPS/UDPS indicating check-sum status, while RX IP/TCP/UDP (good) packets */

Summary of Contents for DM9000A

Page 1: ...CATION NOTES Preliminary 1 Version DM9000A AN V121 November 27 2007 DM9000A 16 8 Bit Ethernet Controller with General Processor Interface Application Notes V1 21 Technical Reference Manual Davicom Semiconductor Inc ...

Page 2: ...M Format 11 3 4 GPIO Pins Setting 15 3 5 Schematic Reference Design 17 3 5 1 Application Schematics for 8 Bit and 16 Bit 17 4 RESET OPERATION AND PHY POWER DOWN MODE 19 4 1 Power On Reset 19 4 2 Software Reset 19 4 3 PHY Power Down Mode 19 4 3 1 GPR PHYPD Setting 20 4 3 2 PHY Register Setting 20 5 HOW TO PROGRAM DM9000A 21 5 1 How to Read Write DM9000A Register 21 5 2 Driver Initializing Steps 22 ...

Page 3: ...ackets 30 5 6 1 Receive Interrupt Service Routine 30 5 6 2 Packet Reception 31 5 6 3 To Check the Packet Status and Length 31 5 6 4 Receive the Packet s Data 32 6 THE OTHERS 33 6 1 How to transmit and receive more than 2048 byte packets 33 6 2 The performance of DM9000A 33 6 3 WOL Wake up on LAN 33 6 4 IP TCP UDP checksums Offload 37 6 5 AUTO MDIX and Application 38 ...

Page 4: ... 1 SIGNAL CONNECTION WITH APROCESSOR INTERFACING 7 FIGURE 2 2 CMD PIN AND PROCESSOR INTERFACE 9 FIGURE 3 1 SCHEMATIC FOR 8 BIT PROCESSOR 17 FIGURE 3 2 SCHEMATIC FOR 16 BIT PROCESSOR 18 FIGURE 5 1 PACKET TRANSMITTING BUFFER 28 FIGURE 5 2 BLOCK DIAGRAM OF THE RECEIVED PACKETS 30 FIGURE 6 1 AUTO MDIX 10BASE T 100BASE TX APPLICATION 38 ...

Page 5: ...7 TABLE 2 1 PIN FUNCTION TABLE FOR PROCESSOR INTERFACE 8 TABLE 3 1 STRAP PIN CONTROLTABLE 10 TABLE 3 2 EEPROM FORMAT IN 16 BIT MODE 11 TABLE 3 3 EEPROM FORMAT IN 8 BIT MODE 13 TBALE 3 4 GENERAL PURPOSE CONTROL REGISTER GPCR TABLE 15 TABLE 3 5 GENERAL PURPOSE REGISTER GPR TABLE 16 ...

Page 6: ...ifferent processors It is good integrated 10 100 Mbps transceiver with AUTO MDIX and IP TCP UDP Checksum Offload The goal of this document is for the embedded design engineers to implement the DM9000A LAN chip on any processor s architecture quickly and successfully with providing the exact reference information and pertaining to many embedded systems The software programming is very simple so use...

Page 7: ...processor micro controller in detail EEPROM 93C46 LC46 AUOT MDIX Transformer RJ 45 25Mhz CMD 32 CS 37 A2 nCS EECS 21 EECK 20 EEDIO 19 DM9000A TXO 7 TXO 8 RXI 3 RXI 4 X1 44 X2 43 IOR 35 IOW 36 INT 34 PWRST 40 INT nRD nWR SD0 SD7 18 10 SD8 SD15 31 22 D0 D7 D8 D15 Power On Reset Figure 2 1 Signal Connection with a Processor Interfacing 2 1 Signals Connection with Processor Bus The DM9000A can interfa...

Page 8: ... 15 31 29 28 27 26 25 24 22 I O DATA Bus 8 15 in 16 bit mode CMD CMD 32 I Command Type When low the access of this command cycle is INDEX port When high the access of this command cycle is DATA port INT INT 34 O Interrupt Request This pin is high active and open collected at default its polarity and its output type can be modified by the EEPROM setting Table 2 1 Pin Function Table for Processor In...

Page 9: ...ATA port is accessed All of these control and status registers in the DM9000A are accessed indirectly by the INDEX DATA ports The command sequence to access the specified control status register is firstly to write the register s address into INDEX port then read write their data through DATA port The following diagram Figure 2 2 is an example for the DM9000A CMD pin connected to an embedded syste...

Page 10: ...e into INDEX port or DATA port So if the IOW and IOR signals in the system are only used by the DM9000A the CS pin can be forced to the active logic level to simplify the system design 3 2 Strap Pins Setting The DM9000A provides the following strap pins Strap pins control list Pin Name Strap Description 20 EECK INT Polarity Type 0 INT active High 1 INT active Low 21 EECS DATA Bus Width 0 DATA 16 b...

Page 11: ...ic target device is IC 93C46 the 1024 bit serial EEPROM EEPROM is 93C46 LC46 such as ATmel Micro chip ATC and CSI All of accesses to the EEPROM are done in words All of the EEPROM addresses in the specification are specified as word addresses The default settings of the DM9000A can be changed by the I O strap pins or the EEPROM bits settings with higher priority The priority for setting the pins p...

Page 12: ...high 1 Processor INT pin is active low Bit 4 0 Processor INT pin is force output 1 Processor INT pin is force open collected Bit 5 0 Processor IOWAIT is active high 1 Processor IOWAIT is active low Bit 6 0 Processor IOWAIT is force output 1 Processor IOWAIT is force open collected Bit 7 0 Processor IO16 is active high 1 Processor IO16 is active low Bit 8 0 Processor IO16 is force output 1 Processo...

Page 13: ...0 Bit 11 10 00 Disable setting of Word 7 Bit 7 01 Accept setting of Word 7 Bit 7 Bit 13 12 00 Disable setting of Word 7 Bit 8 01 Accept setting of Word 7 Bit 8 Bit 15 14 00 Disable setting of Word 7 Bit 15 12 01 Accept setting of Word 7 Bit 15 12 Note The remark is now programming value Vendor ID 4 0A46 2 byte vendor ID Product ID 5 9000 2 byte product ID Pin Control 6 01E7 When Word 3 Bit 3 2 01 ...

Page 14: ...1 LED mode 1 Bit 8 0 The internal PHY is disabled after power on 1 The internal PHY is enabled after power on The GPR REG 1FH Bit 0 is modified from this Bit 8 Bit 11 9 Reserved 0 Bit 13 12 00 LED2 act normal 01 LED2 act as IOWAIT in 16 bit mode only 10 LED2 act as WAKE in 16 bit mode only Bit 14 0 AUTO MDIX OFF 1 AUTO MDIX ON Bit 15 0 LED1 act normal 1 LED1 act as IO16 in 16 bit mode only Note Li...

Page 15: ...s only for the GP6 GP4 pins as the output mode GPCR REG 1EH GPIO interface control Bit Name Default Description 7 RESERVED 0 RO Reserved 6 4 GPC64 111 RO Forced to 1 s only as the output ports of GP6 4 pin 25 26 27 3 1 GPC31 000 RW GP3 1 pin 28 29 31 set to be the input output port 1 the output port represented 0 the input port represented 0 RESERVED 1 RO Reserved Table 3 4 General Purpose Control...

Page 16: ...the pin 29 output high or sets to 0 to enable the pin 29 output low If GP2 is input port the value of GPR Bit 2 is 1 to represent a high signal is received In contract the value of GPR Bit 2 is 0 to represent a low signal is received 1 GPIO1 0 RW If GP1 is output port GPR Bit 1 sets to 1 to enable the pin 31 output high or sets to 0 to enable the pin 31 output low If GP1 is input port the value of...

Page 17: ...0 R0603 R2 510 R0603 R13 4 7K R0603 R12 6 8K1 R0603 C19 0 1UF C0603 C18 0 1UF C0603 Y1 25MHZ 49US XTAL C14 22PF C0603 C 15PF C0603 C20 10UF 16V EC MR05 2 DM9000A 8 16bit U2 DM9000AE LQFP48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 BGRES AVDD25 RX RX RXGND TXGND TX TX AVDD25 SD7 SD6 SD5 SD 4 SD 3 GN D SD 2 ...

Page 18: ...OR INT GND CMD SD8 VDD SD9 SD10 SD11 SD12 SD13 SD14 VDD SD15 EECS EECK EEDIO SD0 SD1 SD2 GND SD3 SD4 SD5 SD6 SD7 VDD25 TX TX TXGND RXGND RX RX VDD25 BGRES C17 0 1UF C0603 R1 10K R0603 C18 0 1UF C0603 C6 330UF 16V CE5MM C9 0 1UF C19 0 01UF 2KV C0603 C8 0 1UF R13 49 9 1 R0603 C7 220UF 16V CE5MM C16 0 1UF C0603 U1 93LC46 PDIP 1 2 3 4 5 6 7 8 CS SK DI DO GND NC NC VCC R8 49 9 1 R0603 C1 0 1UF R12 49 9...

Page 19: ...WRST pin 40 is asserted low for at least 20 ms All of the MAC and PHY registers will be reset to the default values and the hardware strap pins will also be latched The DM9000A is ready after 5 us when this pin is de asserted and then the data will be downloaded from the EEPROM 4 2 Software Reset A software reset can be accomplished by setting RST Bit 0 1 in the network control register NCR REG 00...

Page 20: ...ters the PHYPD bit is used for powering down the internal PHY and it is default high 1 If the internal PHY is desired to be activated the system driver needs to clear this power down bit by writing low 0 to PHYPD in the GPR REG 1FH 4 3 2 PHY Register Setting In the PHY registers the Bit 11 Power down of the basic mode control register BMCR REG 00 can be set high 1 to enable the PHY power down mode...

Page 21: ...t data in the RX TX FIFO SRAM total 16K bytes the address of the register must be written into INDEX port Please refer to the DM9000A datasheet chapter 9 1 about host interface Here are the examples to read and write the DM9000A register Where CMD pin is connected to Processor SA2 UINT16 IOaddr UINT32 IOaddr 0x19000000 for example defined in ARM base HPI BANK3 void iow UINT16 reg UINT8 dataB outb ...

Page 22: ...o the datasheet chapter 6 1 about the NCR setting 4 To set the IMR register REG FFH Bit 7 1 to enable the Pointer Auto Return function which is the memory read write address pointer of the RX TX FIFO SRAM 5 Read the EEPROM data 3 words for the individual Ethernet node address if necessary 6 Write 6 byte Ethernet node address into the Physical Address Registers REG 10H 15H 7 Write Hash Table 8 byte...

Page 23: ...PROM Data The following steps are shown to read data from the serial EEPROM SROM Step 1 write the word address into EPAR REG 0CH Step 2 write command 0x04 into the EEPROM PHY Control Register EPCR REG 0BH to start the SROM READ operation i EPCR REG 0BH EPOS Bit 3 0 select SROM mode this is default 0 ii EPCR REG 0BH ERPRR Bit 2 1 issue READ command Step 3 read EPCR REG 0BH and wait until ERRE Bit 0...

Page 24: ...te of this 16 bit word 5 3 2 HOWTO Write EEPROM Data The following steps are to write data into the SROM Step 1 write the word address into EPAR REG 0CH Step 2 write the data high byte into EE_PHY_H REG 0EH and the low byte to EE_PHY_L Step 3 write command 0x12 into EPCR REG 0BH to start the SROM WRITE operation i EPCR REG 0BH WEP Bit 4 1 enable SROM WRITE operation ii EPCR REG 0BH EPOS Bit 3 0 se...

Page 25: ...0E 56 78 into SROM Word 0 1 2 srom_write 0x00 0xE000 Word 0 low byte 00 high byte E0 srom_write 0x01 0x0E63 Word 1 low byte 63 high byte 0E srom_write 0x02 0x7856 Word 2 low byte 56 high byte 78 void srom_write int offset UINT16 dataW UINT16 i tmpv write the SROM word address into EPAR REG 0CH iow 0x0C offset write the high byte to EE_PHY_H REG 0EH low byte to EE_PHY_L REG 0DH iow 0x0D dataW 0xff ...

Page 26: ...RRE Bit 0 0 ok or just following Step 4 Step 4 wait 5 us maximum then write 0x08 into EPCR REG 0BH to clear READ command Step 5 read the PHY data high byte from EE_PHY_H REG 0EH and the low byte from EE_PHY_L REG 0DH in the EEPROM PHY Data registers For example to read the PHY register of BMCR at address offset 0x00 1 write offset 0 into EPAR REG 0CH Bit 4 0 and 01 b into EPAR REG 0CH Bit 7 6 iow ...

Page 27: ...until ERRE Bit 0 0 ok or just following Step 5 Step 5 wait 5 us maximum then write 0x8 into EPCR REG 0BH to clear WRITE command For example to write data 0x101 into ANAR REG 04 for the 100M Full duplex support 1 write offset 4 into EPAR REG 0CH Bit 4 0 and 01 into EPAR REG 0CH Bit 7 6 iow 0x0C 0x04 0x40 issue PHY address 40H EPAR PHY_ADR 01 b 2 write the PHY high byte 0x01 into EE_PHY_H and low by...

Page 28: ... TXPLH REG FCH for the high byte and TXPLL REG FDH for the low byte The final step is to set the TXREQ Transmit Request Bit 0 in TCR REG 02 for transmitting this packet The DM9000A will generate an interrupt at PTS Bit 1 1 in ISR REG FEH if setting Bit 1 1 in IMR REG FFH and also to set a completion flag to either TX1END Bit 2 1 or TX2END Bit 3 1 in NSR REG 01 in toggle to indicate that the packet...

Page 29: ...ength into TXPLL REG FDH iow 0xFD TX_length 8 0xff write low byte of the TX data length into TXPLH REG FCH Iow 0xFC TX_length 0xff Step 4 start to transmit a packet out iow 0x02 1 set a TX request command TXREQ Bit 0 of TCR REG 02 5 5 2 To Check a Completion Flag If the driver is used the polling interrupt method the program segment can be inserted into the TX routine for detecting a packet transm...

Page 30: ...d byte saves the status information of the received packet The format of the status high byte is the same as RSR REG 06 Please refer to the datasheet ch 6 7 According to this format the received packet can be verified as either a correct packet or an error packet The third and fourth bytes are the length of the received packet The others bytes are the received packet s data or named the RX payload...

Page 31: ...RX_ready 0x2 0 stop interface and wait to reset device iow 0xFF 0x80 stop INT request iow 0xFE 0x0F clear ISR status iow 0x05 0x00 stop RX function u8 device_wait_reset TRUE raise the MAC PHY software reset flag iow 0x00 0x01 it s quick software reset to replace above udelay 10 iow 0x00 NCR_set iow 0xFF 0x80 iow 0x05 RCR_set 1 then re new system variables and counters for dropped and queued packet...

Page 32: ...addr 4 the high byte is the status as RSR REG 06 RX_length inw IOaddr 4 5 6 4 Receive the Packet s Data The read pointer will be increased after reading the memory read command MRCMD REG F2 According to the length of the received packet dump out the RX payload and the 4 byte CRC Here is an example to get the RX packet s data u8 RX_data the data of the received packet with the 4 byte CRC checksum i...

Page 33: ...eed for the DM9000A IOR IOW the performance will be 10ns 10ns 20ns 50Mbps Receive or transmit data 8 50Mbps 400 Mbps 8 bit mode RX TX data at the same time 8 50Mbps 2 200 Mbps Receive or transmit data 16 50Mbps 800 Mbps 16 bit mode RX TX data at the same time 16 50Mbps 2 400 Mbps Note The DM9000A is the 10 100 Mbps Ethernet NIC so the maximum speed is 100 Mbps 6 3 WOL Wake up on LAN The DM9000A LA...

Page 34: ...E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 00 60 6E 90 00 01 another DM9000A TX auto 4 byte CRC appends 2 Link Change If the link status of the internal PHY has been changed the wake up pin will be active For example define NCR 0x00 define WCR 0x0F iow...

Page 35: ...cket 5 byte 1 packet 4 byte 1 Cond 1 byte 1 Cond 0 byte 1 2004h 2008h 200Ch 2010h packet 5 byte 2047 packet 4 byte 2047 Cond 1 byte 2047 Cond 0 byte 2047 3FFCh The format of Condition 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The Condition of packet 0 The Condition of packet 1 The Condition of packet 2 The Condition of packet 3 The format of Condition 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 36: ...MWCMD 0xF8 TX WRITE locking if i 2 outw u16 sample_frame i 1 2 8 IOaddr 4 else outw u16 sample_frame i 1 2 IOaddr 4 16 bit mode set the condition Byte 0 Byte 1 of the Sample Frame in 0x2000 0x3FFD for i 0 sample_ptr 0x2000 i sample_length i sample_ptr 4 set sample_ptr to MWRL as low byte and to MWRH as high byte in DM9000A SRAM iow MWRL sample_ptr 0xff iow MWRH sample_ptr 8 0xff outb 0xF8 IOaddr O...

Page 37: ...us Register RCSCSR REG 32H Bit Name Description 7 UDPS UDP Check Sum Status 0 checksum OK if UDP packet received 6 TCPS TCP Check Sum Status 0 checksum OK if TCP packet received 5 IPS IP Check Sum Status 0 checksum OK if IP packet received 4 UDPP UDP Packet if indicating 1 3 TCPP TCP Packet if indicating 1 2 IPP IP Packet if indicating 1 1 RCSEN Receive Check Sum Enable Checking When set the check...

Page 38: ... the transformer to the DM9000A Figure 6 1 AUTO MDIX 10Base T 100Base TX Application The DM9000A is default turning on AUTO MDIX feature and there are two ways to disable AUTO MDIX function 1 To set the SROM Word 7 Wake up Mode Control Bit 14 1 then zero to re load it srom_write 0x07 0x180 PHY power on but disable Auto MDIX setting into SROM iow 0x0B 0x20 REEP Bit 5 of EPCR REG 0BH to re load EEPR...

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