DM9000A
APPLICATION NOTES
Preliminary 26
Version: DM9000A-AN-V121
November 27, 2007
5.4 How to Read/ Write PHY Register
The DM9000A PHY supports only 32 registers, which are mapped to EPAR (REG. 0CH) Bit
[4:0]. The default value of EPAR (REG. 0CH) PHY_ADR Bit [7:6] is "01" to select the PHY
mode. Please refer to the datasheet ch.6.12~6.14 about the EEPROM&PHY registers setting.
5.4.1 HOWTO Read PHY Register
The following steps are shown to read data from the PHY register:
Step 1: write the PHY register offset into EPAR REG. 0CH Bit [4:0], and the PHY address
"01"b into EPAR REG. 0CH Bit [7:6].
Step 2: write command = 0x0C into EPCR REG. 0BH to start the PHY + READ operation:
i. EPCR (REG. 0BH) EPOS Bit [3] = 1: select PHY mode (0: select SROM, see ch.5.3)
ii. EPCR (REG. 0BH) ERPRR Bit [2] = 1: issue READ command.
Step 3: read EPCR REG. 0BH and wait until ERRE Bit [0] = 0 ok, or just following Step 4.
Step 4: wait 5 us maximum, then write "0x08" into EPCR REG. 0BH to clear READ command.
Step 5: read the PHY data high byte from EE_PHY_H REG. 0EH, and the low byte from
EE_PHY_L REG. 0DH in the EEPROM&PHY Data registers.
For example, to read the PHY register of BMCR at address offset = 0x00:
1.
write offset = 0 into EPAR REG. 0CH Bit [4:0], and "01"b into EPAR REG. 0CH Bit[7:6]
iow ( 0x0C, ( 0x00 | 0x40 ) );/* issue PHY 40H (EPAR PHY_ADR = "01"b) */
2. write the PHY + READ command = 0x0C into EPCR REG. 0BH
iow ( 0x0B, ( 0x04 | 0x08 ) );
3. wait until EPCR REG. 0B ERRE Bit [0] = 0 ok, or just following Step 4
do { udelay ( 1 ); i++; } while ( ( i < 50 ) && ( inb ( 4 ) & 1 ) );
4.
delay 5 us maximum, then write "0x8" into EPCR REG. 0BH to clear it and keep PHY
udelay ( 5 );
/* wait 1~5 us for the PHY+ READ command completion */
iow ( 0x0B, 0x08 );
/* clear this PHY "READ" command */
5.
read the high byte from EE_PHY_H REG. 0EH, and the low byte from EE_PHY_L
(UINT8) phy[offset*2+1] = ior ( 0x0E );
/* the high byte of this 16-bit word */
(UINT8) phy[offset*2] = ior ( 0x0D );
/* the low byte of this 16-bit word */
