DM9000A
APPLICATION NOTES
Preliminary 10
Version: DM9000A-AN-V121
November 27, 2007
3 System Hardware Design
3.1 How to Select Chip
In the command cycle, the DM9000A is accessed by CS pin cooperated with IOR or IOW pins.
These pins are low active at default, while their polarity can be modified by EEPROM setting
to suit for the application of various processor types.
Both of CS pin and IOW/ IOR pin should be active to write/ read the value into INDEX port or
DATA port. So, if the IOW and IOR signals in the system are only used by the DM9000A, the
CS pin can be forced to the active logic level to simplify the system design.
3.2 Strap Pins Setting
The DM9000A provides the following strap pins:
Strap pins control list:
Pin Name
Strap
Description
20 EECK
INT
Polarity
Type
0: INT active High
1: INT active Low
21
EECS
DATA Bus Width
0: DATA 16-bit mode
1: DATA 8-bit mode
25 GP6 INT
Output
Type
available in 8-bit mod
e
only
0: INT Force-Output mode
1: INT Open-Drain mode
Table 3.1 Strap Pin Control Table
Note: "1" means pull-high with the 10K Ohm resistor, and "0" means floating (default).
