Principles of Operation
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• Digital Event trigger
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A digital event trigger occurs when the
DT9820 Series module detects a high-to-low transition on a
digital input line. Depending on the digital input line, the A/D
conversion is either started or stopped, as shown in
When the operation is stopped, the driver empties the data
buffers, sends the data to the host application program, and
reports a trigger error message. It is up to your program to
manage this message appropriately for your application. For
example, if you want to restart the operation when another
digital event trigger occurs, you might want to set up new A/D
buffers when the trigger error message occurs.
Using software, specify the trigger source as a digital event
trigger. Refer to the example programs on the Data Acq OMNI
CD for an example of using a digital event trigger.
Note:
All the digital inputs must be in the high state before the
DT9820 Series module can detect a high-to-low transition on the
digital input lines.
Analog Input Conversion Modes
DT9820 Series function modules support the following conversion
modes:
• Single-value operations are the simplest to use but offer the least
flexibility and efficiency. Using software, you can specify the
range, gain, and analog input channel, and acquire the data from
that channel. The data is returned immediately. For a single-value
operation, you cannot specify a clock source, trigger source, or
buffer. Single-value operations use a clock frequency of 60 Hz or
50 Hz to acquire data; this provides the best line frequency
selection.
Summary of Contents for DT9820 Series
Page 1: ...DT9820 Series UM 18221 B User s Manual...
Page 4: ......
Page 7: ...Contents vii Appendix B Connector Pin Assignments 81 Index 87...
Page 8: ...Contents viii...
Page 13: ...1 1 Overview Features 2 Supported Software 4 Accessories 6...
Page 40: ...Chapter 2 28...
Page 41: ...29 3 Supported Device Driver Capabilities...
Page 52: ...Chapter 3 40...
Page 69: ...57 5 Calibration Running the Calibration Utility 59 Calibrating the Analog Output Subsystem 60...
Page 74: ...Chapter 5 62...
Page 84: ...Chapter 6 72...
Page 85: ...73 A Specifications...
Page 93: ...81 B Connector Pin Assignments...
Page 98: ...Appendix B 86...
Page 106: ...Index 94...
Page 108: ......
Page 112: ...Data Translation Support Policy...