PCIe-FRM11 User’s Manual (Rev 1.4)
-
20
- http://www.daqsystem.com
[Description of SW1]
PCIe-FRM11 board is designed of four maximum PCIe-FRM11 boards at the same time so as
usable. Distribution of each board sets it up through 4 pin switch (SW1) in a board.
[Figure 3-11. SW1 pin-out]
[Table 5. SW1 Description]
1
2
Description
OFF
OFF
Board No. 0
ON
OFF
Board No. 1
OFF
On
Board No. 2
On
ON
Board No. 3
[J4 Connector (2Pin Header, 2.54mm)]
3.3V external DC power connector. It is a power source for FPGA installation and is not normally
used.
[JP3 Connector]
JP3 is a Joint Test Action Group (JTAG) connector used to update the board's FPGA program. Do
not use it when operating the board normally.
