Dalsa PC2-Comp Express OC-P2EM-COMP0, User Manual

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Theory of Operation PC2-Comp Express
Onboard Memory
Onboard memory behaves as a temporary buffer between the camera interface and the host PCIe
system. The onboard memory for image frame buffers is 8MB. Maximum captured frame size is
limited by onboard memory: one incoming frame must fit into onboard memory. Onboard memory
allows capture from cameras requiring a bandwidth exceeding the PCIe x1 practical maximum of
200MB/second. It also compensates for latencies introduced by any other PCI bus master within the
host system.
DMA Controller
The DMA controller reads data from onboard memory and sends this data to the PCIe bus. It uses
scatter-gather support to reduce CPU usage to a minimum and retrieves the buffer descriptor list from
host memory. Generally host system memory allocated for frame buffers is virtually contiguous but
physically scattered throughout all available memory.
The DMA controller is also responsible for other image manipulation functions as described below.
Image Flip Operations
The PC2-Comp Express DMA controller performs image flip operations vertically.
1 2
3 4
3 4
1 2
Figure 6:Vertical Image Flip
Events and Status
The PC2-Comp Express frame grabber provides acquisition and transfer events that allow an
application to accurately monitor acquisition/transfer status, one of the many elements that make up
the "trigger-to-image reliability" model supported by the
Acquisition and Control Unit (ACU). See
" Event-Related Definitions" on page 25. The events are grouped into two families:
1. Acquisition Events
2. Transfer Events
Acquisition events are related to the acquisition module. They provide feedback on the image
digitization phase. The following block diagram illustrates the acquisition process.