DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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THIR: TRANSMIT HDLC INFORMATION REGISTER (Address = B6 Hex)
(MSB)
(LSB)
— — — — —
TEMPTY
TFULL
TUDR
SYMBOL
POSITION
NAME AND DESCRIPTION
— THIR.7
Not Assigned.
Could be any value when read.
— THIR.6
Not Assigned.
Could be any value when read.
— THIR.5
Not Assigned.
Could be any value when read.
— THIR.4
Not Assigned.
Could be any value when read.
— THIR.3
Not Assigned.
Could be any value when read.
TEMPTY THIR.2
Transmit FIFO Empty.
A real-time bit that is set high when the FIFO is
empty.
TFULL THIR.1
Transmit FIFO Full.
A real-time bit that is set high when the FIFO is
full.
TUDR THIR.0
Transmit FIFO Underrun.
Set when the transmit FIFO empties out
without the TEOM control bit being set. An abort is automatically sent.
Note: The TUDR bit is latched and is cleared when read.
THFR: TRANSMIT HDLC FIFO REGISTER (Address = B7 Hex)
(MSB)
(LSB)
HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0
SYMBOL
POSITION
NAME AND DESCRIPTION
HDLC7 THFR.7
HDLC Data Bit 7.
MSB of a HDLC packet data byte.
HDLC6 THFR.6
HDLC Data Bit 6.
HDLC5 THFR.5
HDLC Data Bit 5.
HDLC4 THFR.4
HDLC Data Bit 4.
HDLC3 THFR.3
HDLC Data Bit 3.
HDLC2 THFR.2
HDLC Data Bit 2.
HDLC1 THFR.1
HDLC Data Bit 1.
HDLC0 THFR.0
HDLC Data Bit 0.
LSB of a HDLC packet data byte.
