DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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HSR: HDLC STATUS REGISTER (Address = B1 Hex)
(MSB)
(LSB)
FRCL RPE RPS RHALF RNE THALF TNF TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
FRCL HSR.7
Framer Receive Carrier Loss.
Set when 255 (or 2048 if CCR3.0 = 1)
consecutive zeros have been detected at RPOSI and RNEGI.
RPE HSR.6
Receive Packet End.
Set when the HDLC controller detects either the
finish of a valid message (i.e., CRC check complete) or when the
controller has experienced a message fault such as a CRC checking error,
or an overrun condition, or an abort has been seen. The setting of this bit
prompts the user to read the RHIR register for details.
RPS HSR.5
Receive Packet Start
. Set when the HDLC controller detects an opening
byte. The setting of this bit prompts the user to read the RHIR register for
details.
RHALF HSR.4
Receive FIFO Half Full.
Set when the receive 64-byte FIFO fills beyond
the halfway point. The setting of this bit prompts the user to read the
RHIR register for details.
RNE HSR.3
Receive FIFO Not Empty.
Set when the receive 64-byte FIFO has at
least one byte available for a read. The setting of this bit prompts the user
to read the RHIR register for details.
THALF HSR.2
Transmit FIFO Half Empty.
Set when the transmit 64-byte FIFO
empties beyond the halfway point. The setting of this bit prompts the user
to read the THIR register for details.
TNF HSR.1
Transmit FIFO Not Full.
Set when the transmit 64-byte FIFO has at
least one byte available. The setting of this bit prompts the user to read the
THIR register for details.
TMEND HSR.0
Transmit Message End.
Set when the transmit HDLC controller has
finished sending a message. The setting of this bit prompts the user to read
the THIR register for details.
Note: The RPE, RPS, and TMEND bits are latched and are cleared when read.
