DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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3.1.6. Line
Interface
Pins
Signal Name:
MCLK
Signal Description:
Master Clock Input
Signal Type:
Input
A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally
for both clock/data recovery and for jitter attenuation. A quartz crystal of 2.048MHz may be applied
across MCLK and XTALD instead of the TTL level clock source.
Signal Name:
XTALD
Signal Description:
Quartz Crystal Driver
Signal Type:
Output
A quartz crystal of 2.048MHz may be applied across MCLK and XTALD instead of a TTL level clock
source at MCLK. Leave open circuited if a TTL clock source is applied at MCLK.
Signal Name:
8XCLK
Signal Description:
Eight-Times Clock
Signal Type:
Output
A 16.384MHz clock that is frequency locked to the 2.048MHz clock provided from the clock/data
recovery block (if the jitter attenuator is enabled on the receive side) or from the TCLKI pin (if the jitter
attenuator is enabled on the transmit side). Can be internally disabled via TEST2 register if not needed.
Signal Name:
LIUC
Signal Description:
Line Interface Connect
Signal Type:
Input
Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circuitry to the
framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When
LIUC is tied high, the TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.
Signal Name:
RTIP and RRING
Signal Description:
Receive Tip and Ring
Signal Type:
Input
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the E1 line. See
Section
for details.
Signal Name:
TTIP and TRING
Signal Description:
Transmit Tip and Ring
Signal Type:
Output
Analog line-driver outputs. These pins connect via a step-up transformer to the E1 line. See Section
for details.
