Dallas Semiconductor MAXIM DS21354 Manual Download

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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

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Figure 20-12. Transmit System Side AC Timing

Figure 20-13. Transmit Line Interface Side AC Timing

TSYSCLK

TSER

TCHCLK / CO

TSSYNC

TCHBLK

t D3

tD3

tSU

tHD

Notes:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.

tSC

tWC

TCLKO

TPOSO, TNEGO

tDD

TCLKI

TPOSI, TNEGI

tHD

tSU

Summary of Contents for MAXIM DS21354

Page 1: ...E1 specifications including ITU T G 703 G 704 G 706 G 823 G 732 and I 431 ETS 300 011 300 233 and 300 166 as well as CTR12 and CTR4 PIN CONFIGURATION FEATURES Complete E1 CEPT PCM 30 ISDN PRI Transce...

Page 2: ...RONIZATION AND RESYNCHRONIZATION 32 5 3 FRAMER LOOPBACK 36 5 4 AUTOMATIC ALARM GENERATION 38 5 5 REMOTE LOOPBACK 40 5 6 LOCAL LOOPBACK 40 6 STATUS AND INFORMATION REGISTERS 43 6 1 CRC4 SYNC COUNTER 45...

Page 3: ...GISTER DESCRIPTION 73 15 LINE INTERFACE FUNCTIONS 80 15 1 RECEIVE CLOCK AND DATA RECOVERY 81 15 2 TRANSMIT WAVESHAPING AND LINE DRIVING 81 15 3 JITTER ATTENUATOR 82 15 4 PROTECTED INTERFACES 86 15 5 R...

Page 4: ...de 103 Figure 18 7 Transmit Side Timing 104 Figure 18 8 Transmit Side Boundary Timing with Elastic Store Disabled 104 Figure 18 9 Transmit Side 1 544MHz Boundary Timing with Elastic Store Enabled 105...

Page 5: ...able 6 1 Alarm Criteria 46 Table 14 1 HDLC Controller Register List 70 Table 15 1 Line Build Out Select in LICR for the DS21554 81 Table 15 2 Line Build Out Select in LICR for the DS21354 82 Table 15...

Page 6: ...in a separate PCM data stream Signaling freezing Interrupt generated on change of signaling data 9 Improved receive sensitivity 0 to 43dB 1 1 Per channel code insertion in both transmit and receive p...

Page 7: ...The transmit side framer is totally independent from the receive side in both the clock requirements and characteristics Data off a backplane can be passed through a transmit side elastic store if ne...

Page 8: ...ed Receive Monitor Mode section 041599 Added section on Protected Interfaces 050799 Corrected pin number and description of FMS in JTAG section 072999 Added list of tables and figures 091499 Added 10m...

Page 9: ...er transmit or receive path Receive Line I F Clock Data Recovery RRING RTIP Remote Loopback VCO PLL MCLK 8XCLK 8MCLK 8 192MHz Clock Synthesizer 32 768MHz 16 384 MHz XTALD RCLK RPOSO RNEGO RNEGI RPOSI...

Page 10: ...g Input 18 RVDD Receive Analog Positive Supply 19 20 24 RVSS Receive Analog Signal Ground 21 MCLK I Master Clock Input 22 XTALD O Quartz Crystal Driver 25 INT O Interrupt Active Low 29 TTIP O Transmit...

Page 11: ...s Bit 2 69 A3 I Address Bus Bit 3 70 A4 I Address Bus Bit 4 71 A5 I Address Bus Bit 5 72 A6 I Address Bus Bit 6 73 ALE AS A7 I Address Latch Enable Address Bus Bit 7 74 RD DS I Read Input Data Strobe...

Page 12: ...4 63 D5 AD5 I O Data Bus Bit 5 Address Data Bus Bit 5 64 D6 AD6 I O Data Bus Bit 6 Address Data Bus Bit 6 65 D7 AD7 I O Data Bus Bit 7 Address Data Bus Bit 7 44 61 81 83 DVDD Digital Positive Supply 4...

Page 13: ...og Signal Ground 33 TCHBLK O Transmit Channel Block 53 TCHCLK O Transmit Channel Clock 46 TCLK I Transmit Clock 40 TCLKI I Transmit Clock Input 41 TCLKO O Transmit Clock Output 50 TDATA I Transmit Dat...

Page 14: ...annel Block Signal Type Output A user programmable output that can be forced high or low during any of the 32 E1 channels Synchronous with TCLK when the transmit side elastic store is disabled Synchro...

Page 15: ...t use the transmit side elastic store Signal Name TSIG Signal Description Transmit Signaling Input Signal Type Input When enabled this input will sample signaling bits for insertion into outgoing PCM...

Page 16: ...ransmit Positive Data Input Signal Type Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line Can be internally connected to TPOSO by tying the LIUC pin high TPOSI...

Page 17: ...hat can be forced high or low during any of the 32 E1 channels Synchronous with RCLK when the receive side elastic store is disabled Synchronous with RSYSCLK when the receive side elastic store is ena...

Page 18: ...lications that do not use the receive side elastic store See Section 17 for details on 4 096MHz and 8 192MHz operation using the Interleave Bus Option Signal Name RSIG Signal Description Receive Signa...

Page 19: ...ffered recovered clock from the T1 line This pin is normally tied to RCLKI Signal Name RPOSI Signal Description Receive Positive Data Input Signal Type Input Sampled on the falling edge of RCLKI for d...

Page 20: ...ow for normal operation Useful in board level testing Signal Name MUX Signal Description Bus Operation Signal Type Input Set low to select nonmultiplexed bus operation Set high to select multiplexed b...

Page 21: ...Name CS Signal Description Chip Select Signal Type Input Must be low to read or write to the device CS is an active low signal Signal Name ALE AS A7 Signal Description Address Latch Enable Address St...

Page 22: ...Test Clock Signal Signal Type Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge Signal Name JTDI Signal Description IEEE 1149 1 Test Data Input S...

Page 23: ...the jitter attenuator is enabled on the receive side or from the TCLKI pin if the jitter attenuator is enabled on the transmit side Can be internally disabled via TEST2 register if not needed Signal...

Page 24: ...e tied to the DVDD and TVDD pins Signal Name TVDD Signal Description Transmit Analog Positive Supply Signal Type Supply 5 0V 5 DS21554 or 3 3V 5 DS21354 Should be tied to the RVDD and DVDD pins Signal...

Page 25: ...AS Error Count 2 EBCR1 05 R E Bit Count 2 EBCR2 06 R W Status 1 SR1 07 R W Status 2 SR2 08 R W Receive Information RIR 09 Not used set to 00h 0A Not used set to 00h 0B Not used set to 00h 0C Not used...

Page 26: ...39 R Receive Signaling 10 RS10 3A R Receive Signaling 11 RS11 3B R Receive Signaling 12 RS12 3C R Receive Signaling 13 RS13 3D R Receive Signaling 14 RS14 3E R Receive Signaling 15 RS15 3F R Receive S...

Page 27: ...nnel 9 TC9 69 R W Transmit Channel 10 TC10 6A R W Transmit Channel 11 TC11 6B R W Transmit Channel 12 TC12 6C R W Transmit Channel 13 TC13 6D R W Transmit Channel 14 TC14 6E R W Transmit Channel 15 TC...

Page 28: ...ve Channel 26 RC26 9A R W Receive Channel 27 RC27 9B R W Receive Channel 28 RC28 9C R W Receive Channel 29 RC29 9D R W Receive Channel 30 RC30 9E R W Receive Channel 31 RC31 9F R W Receive Channel 32...

Page 29: ...1 RDC1 B9 R W Receive HDLC DS0 Control Register 2 RDC2 BA R W Transmit HDLC DS0 Control Register 1 TDC1 BB R W Transmit HDLC DS0 Control Register 2 TDC2 BC Not used set to 00h BD Not used set to 00h...

Page 30: ...e variations of these bits and the associated SCT Table 5 1 Device ID Bit Map SCT T1 E1 BIT 6 BIT 5 BIT 4 DS2152 0 0 0 0 DS21352 0 0 0 1 DS21552 0 0 1 0 DS2154 1 0 0 0 DS21354 1 0 0 1 DS21554 1 0 1 0...

Page 31: ...tiframe Function Only used if the RSYNC pin is programmed in the multiframe mode RCR1 6 1 0 RSYNC outputs CAS multiframe boundaries 1 RSYNC outputs CRC4 multiframe boundaries RSM RCR1 6 RSYNC Mode Sel...

Page 32: ...E LEVEL SYNC CRITERIA RESYNC CRITERIA ITU SPEC FAS FAS present in frame N and N 2 and FAS not present in frame N 1 Three consecutive incorrect FAS received Alternate RCR1 2 1 the above criteria is met...

Page 33: ...Set to one to have RLCLK pulse at the Sa6 bit position set to zero to force RLCLK low during Sa6 bit position See Section 18 1 for timing details Sa5S RCR2 4 Sa5 Bit Select Set to one to have RLCLK p...

Page 34: ...time slot 16 from TS0 to TS15 registers TUA1 TCR1 4 Transmit Unframed All Ones 0 transmit data normally 1 transmit an unframed all one s code at TPOSO and TNEGO TSiS TCR1 3 Transmit International Bit...

Page 35: ...LINK pin set to zero to not source the Sa6 bit See Section 18 2 for timing details Sa5S TCR2 4 Sa5 Bit Select Set to one to source the Sa5 bit from the TLINK pin set to zero to not source the Sa5 bit...

Page 36: ...signaling mode 1 CCS signaling mode RHDB3 CCR1 2 Receive HDB3 Enable 0 HDB3 disabled 1 HDB3 enabled RG802 CCR1 1 Receive G 802 Enable See Section 18 for details 0 do not force RCHBLK high during bit...

Page 37: ...R2 3 RSER Control 0 allow RSER to output data as received under all conditions 1 force RSER to one under loss of frame alignment conditions LOTCMC CCR2 2 Loss of Transmit Clock Mux Control Determines...

Page 38: ...er will either force an AIS alarm When automatic RAI generation is enabled CCR2 4 1 the framer monitors the receive side to determine if any of the following conditions are present loss of receive fra...

Page 39: ...ER i e Per Cannel Loopback function CCR3 4 Not Assigned Should be set to zero when written to RSRE CCR3 3 Receive Side Signaling Reinsertion Enable See Section 10 2 for details 0 do not reinsert signa...

Page 40: ...3 TCM2 CCR4 2 Transmit Channel Monitor Bit 2 TCM1 CCR4 1 Transmit Channel Monitor Bit 1 TCM0 CCR4 0 Transmit Channel Monitor Bit 0 LSB of the channel decode 5 5 Remote Loopback When CCR4 7 is set to...

Page 41: ...rupted Should be toggled after RSYSCLK has been applied and is stable Must be cleared and set again for a subsequent align See Section 12 for details TESA CCR5 5 Transmit Elastic Store Align Setting t...

Page 42: ...or a 2 048MHz synchronization signal Section 10 of G 703 This control has no affect on the line interface transmitter 0 line receiver configured to support a normal E1 signal 1 line receiver configure...

Page 43: ...rs will be immediately followed by a read of the same register The read result should be logically ANDed with the mask byte that was just written and this value should be written back into the same re...

Page 44: ...teria Met Event FASRC Set when three consecutive FAS words are received in error Note During a CRC resync the FAS synchronizer is brought online to verify the FAS alignment If during this process a FA...

Page 45: ...e frames This alarm is not disabled in the CCS signaling mode Both RSA1 and RSA0 will be set if a change in signaling is detected RDMA SR1 6 Receive Distant MF Alarm Set when bit 6 of time slot 16 in...

Page 46: ...l MF time slot 16 contains at least a single one G 732 5 2 RDMA Receive Distant Multiframe Alarm bit 6 in time slot 16 of frame 0 set to one for two consecutive MF bit 6 in time slot 16 of frame 0 set...

Page 47: ...mit multiframe boundaries Used to alert the host that signaling data needs to be updated SEC SR2 4 One Second Timer Set on increments of one second based on RCLK If CCR2 7 1 then this bit will be set...

Page 48: ...arm 0 interrupt masked 1 interrupt enabled RSA0 IMR1 5 Receive Signaling All Zeros Signaling Change 0 interrupt masked 1 interrupt enabled RSLIP IMR1 4 Receive Elastic Store Slip Occurrence 0 interrup...

Page 49: ...0 interrupt masked 1 interrupt enabled TMF IMR2 5 Transmit Multiframe 0 interrupt masked 1 interrupt enabled SEC IMR2 4 One Second Timer 0 interrupt masked 1 interrupt enabled TAF IMR2 3 Transmit Ali...

Page 50: ...ounter that records either BiPolar Violations BPVs or Code Violations CVs If CCR2 6 0 then the VCR counts bipolar violations Bipolar violations are defined as consecutive marks of the same polarity In...

Page 51: ...02 are the most significant bits of the 12 bit FAS error counter 7 3 E Bit Counter E bit Count Register 1 EBCR1 is the most significant word and EBCR2 is the least significant word of a 10 bit counter...

Page 52: ...nce the maximum FAS word error count in a one second period is 4000 this counter cannot saturate FASCR1 FAS ERROR COUNT REGISTER 1 Address 02 Hex FASCR2 FAS ERROR COUNT REGISTER 2 Address 04 Hex MSB L...

Page 53: ...e decimal decode of the appropriate E1 channel For example if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction need to be monitored then the following values would b...

Page 54: ...Bit 8 LSB of the DS0 channel last bit to be transmitted CCR5 COMMON CONTROL REGISTER 5 Address AA Hex Repeated here from Section 5 for convenience MSB LSB LIRST RESALGN TESALGN RCM4 RCM3 RCM2 RCM1 RC...

Page 55: ...B1 RDS0M 7 Receive DS0 Channel Bit 1 MSB of the DS0 channel first bit received B2 RDS0M 6 Receive DS0 Channel Bit 2 B3 RDS0M 5 Receive DS0 Channel Bit 3 B4 RDS0M 4 Receive DS0 Channel Bit 4 B5 RDS0M...

Page 56: ...eet For example voice channel 1 is associated with time slot 1 Channel 2 and voice channel 30 is associated with time slot 31 Channel 32 There is a set of 16 registers for the receive side RS1 to RS16...

Page 57: ...fore the data is lost TS1 TO TS16 TRANSMIT SIGNALING REGISTERS Address 40 to 4F Hex MSB LSB 0 0 0 0 X Y X X TS1 40 A 1 B 1 C 1 D 1 A 16 B 16 C 16 D 16 TS2 41 A 2 B 2 C 2 D 2 A 17 B 17 C 17 D 17 TS3 42...

Page 58: ...them over a four multiframe buffer and outputting them in a serial PCM fashion on a channel by channel basis at the RSIG output This mode is always enabled In this mode the receive elastic store may...

Page 59: ...ourced from TSER or TSIG if CCR3 2 1 and a one implies that signaling data for that channel is to be sourced from the Transmit Signaling TS registers See definition below TCBR1 TCBR2 TCBR3 TCBR4 DEFIN...

Page 60: ...frame When these bits are set to a one the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register TIDR The Transmit Idle Registers TIRs have an alternate...

Page 61: ...be placed into each of the 32 E1 channels TC1 TO TC32 TRANSMIT CHANNEL REGISTERS Address 60 to 7F Hex For brevity only channel one is shown see for other register address MSB LSB C7 C6 C5 C4 C3 C2 C1...

Page 62: ...1 for other register address MSB LSB C7 C6 C5 C4 C3 C2 C1 C0 RC1 80 SYMBOL POSITION NAME AND DESCRIPTION C7 RC1 7 MSB of the Code this bit is sent first to the backplane C0 RC1 0 LSB of the Code this...

Page 63: ...NG REGISTERS Address 2B to 2E Hex MSB LSB CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RCBR1 2B CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RCBR2 2C CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RCBR3 2D CH32 CH31 CH30 CH29...

Page 64: ...CH18 CH3 CH17 CH2 CH16 CH1 1 1 TCBR1 22 CH22 CH7 CH21 CH6 CH20 CH5 CH19 CH4 TCBR2 23 CH26 CH11 CH25 CH10 CH24 CH9 CH23 CH8 TCBR3 24 CH30 CH15 CH29 CH14 CH28 CH13 CH27 CH12 TCBR4 25 These bits should b...

Page 65: ...ulse on frame multiframe boundaries RCR1 5 0 If the user wishes to obtain pulses at the frame boundary then RCR1 6 must be set to zero If the user wishes to have pulses occur at the multiframe boundar...

Page 66: ...he Sa bits through the framer without them being altered then the device should be set up to source all five Sa bits via the TLINK pin and the TLINK pin should be tied to the TSER pin Si bits can be i...

Page 67: ...E AND DESCRIPTION Si RNAF 7 International Bit 1 RNAF 6 Frame Non Alignment Signal Bit A RNAF 5 Remote Alarm Sa4 RNAF 4 Additional Bit 4 Sa5 RNAF 3 Additional Bit 5 Sa6 RNAF 2 Additional Bit 6 Sa7 RNAF...

Page 68: ...e Transmit Sa Bit Control Register TSaCR can be programmed to insert both Si and Sa data Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 2 SR2 5...

Page 69: ...the transmit data stream Sa4 TSaCR 4 Additional Bit 4 Insertion Control Bit 0 do not insert data from the TSa4 register into the transmit data stream 1 insert data from the TSa4 register into the tran...

Page 70: ...r A brief description of the registers is shown in Table 14 1 Table 14 1 HDLC Controller Register List NAME FUNCTION HDLC Control Register HCR HDLC Status Register HSR HIMR Interrupt Mask Register HIM...

Page 71: ...oes not wish to obtain the latest information on When a one is written to a bit location the read register will be updated with current value and it will be cleared When a zero is written to a bit pos...

Page 72: ...packet if POK 1 accept the packet a Disable RPE RNE or RHALF interrupt enable RPS interrupt and return to step 1 14 3 2 Example Transmit an HDLC Message 1 Make sure HDLC controller is done sending any...

Page 73: ...bsequent reset TABT HCR 3 Transmit Abort A 0 to 1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags idle until a new packet is initiated by...

Page 74: ...ster for details RHALF HSR 4 Receive FIFO Half Full Set when the receive 64 byte FIFO fills beyond the halfway point The setting of this bit prompts the user to read the RHIR register for details RNE...

Page 75: ...Packet End 0 interrupt masked 1 interrupt enabled RPS HIMR 5 Receive Packet Start 0 interrupt masked 1 interrupt enabled RHALF HIMR 4 Receive FIFO Half Full 0 interrupt masked 1 interrupt enabled RNE...

Page 76: ...he receive FIFO at RHFR is the last byte of a valid message and hence no abort was seen no overrun occurred and the CRC was correct CBYTE RHIR 1 Closing Byte Set when the byte available for reading in...

Page 77: ...ULL THIR 1 Transmit FIFO Full A real time bit that is set high when the FIFO is full TUDR THIR 0 Transmit FIFO Underrun Set when the transmit FIFO empties out without the TEOM control bit being set An...

Page 78: ...elect Bit 4 MSB of the DS0 channel select RD3 RDC1 3 DS0 Channel Select Bit 3 RD2 RDC1 2 DS0 Channel Select Bit 2 RD1 RDC1 1 DS0 Channel Select Bit 1 RD0 RDC1 0 DS0 Channel Select Bit 0 LSB of the DS0...

Page 79: ...utilize the TCHBLK control registers to select which DS0 channels to use TD4 TDC1 4 DS0 Channel Select Bit 4 MSB of the DS0 channel select TD3 TDC1 3 DS0 Channel Select Bit 3 TD2 TDC1 2 DS0 Channel Se...

Page 80: ...Bit 2 Sets the transmitter build out see Table 15 1 and Table 15 2 L1 LICR 6 Line Build Out Select Bit 1 Sets the transmitter build out see Table 15 1 and Table 15 2 L0 LICR 5 Line Build Out Select Bi...

Page 81: ...circuitry If the jitter attenuator is placed in the receive path as is the case in most applications the jitter attenuator restores the RCLK to being close to 50 duty cycle Please see the Receive AC...

Page 82: ...tenuator The DS21354 DS21554 contain an on board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register LICR The 128 bit mode is...

Page 83: ...TRING E1 Receive Line E1 Transmit Line DS21354 DS21554 0 47 nonpolarized Rr 0 1mF Rt Rt 1 1 N 1 See Note 1 Rr 2 048MHz MCLK DVDD DVSS 0 1 RVDD RVSS 0 1 TVDD TVSS 0 1 VDD 0 01 10 NOTE 1 ALL CAPACITORS...

Page 84: ...CY Hz UNIT INTERVALS UIpp 1K 100 10 1 0 1 10 100 1K 10K 100K DS21354 DS21554 Tolerance 1 Minimum Tolerance Level as per ITU G 823 40 1 5 0 2 20 2 4K 18K FREQUENCY Hz 0dB 20dB 40dB 60dB 1 10 100 1K 10K...

Page 85: ...Transmit Waveform Template 0 0 1 0 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 0 TIME ns SCALED AMPLITUDE 50 100 150 200 250 50 100 150 200 250 269ns 194ns 219ns in 75 ohm systems 1 0 on the sca...

Page 86: ...xamples in this data sheet are for Secondary Over Voltage Protection schemes for the line terminating equipment Primary protection is typically provided by the network service provide and is external...

Page 87: ...LECTION OF THESE COMPONENTS REFER TO THE SEPARATE APPLICATION NOTES ON SECONDARY OVERVOLTAGE PROTECTION AND T1 E1 NETWORK INTERFACE DESIGN AVAILABLE ON OUR WEBSITE AT WWW MAXIM IC COM APPNOTEINDEX RTI...

Page 88: ...N FUSE 1 25A SLO BLO LITTLEFUSE V2301 25 S SEMTECH LC01 6 6V LOW CAPACITANCE TVS X1 X2 TRANSPOWER PT314 LOW DCR RTIP RRING TTIP TRING Receive Line DS21354 S C1 D1 D2 D3 D4 1 1 Fuse Fuse Transmit Line...

Page 89: ...rcome the resistive loss of a monitor connection This is typically a purely resistive loss gain and should not be confused with the cable loss characteristics of an E1 transmission line Via the TEST3...

Page 90: ...TAP TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The DS21354 DS21554 are enhanced versions of the DS2152 and are backward pin compatible T...

Page 91: ...Transceivers 91 of 124 Figure 16 1 JTAG Functional Block Diagram V BOUNDARY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER JTDI JTMS JTCLK JTRST JTDO V V TEST ACCESS PORT M...

Page 92: ...JTMS is LOW or it will go to the Exit1 DR state if JTMS is HIGH Shift DR The test data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one sta...

Page 93: ...ith JTMS HIGH will move the controller to the Exit1 IR state A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift IR state while moving data one stage thorough the instruction sh...

Page 94: ...6 2 TAP Controller State Diagram 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 Select DR Scan Capture DR Shift DR Exit DR Pause DR Exit2 DR Update DR Select IR Scan Capture IR Shift IR...

Page 95: ...he boundary scan register without interfering with the normal operation of the device by using the Capture DR state SAMPLE PRELOAD also allows the device to shift data into the boundary scan register...

Page 96: ...requires a minimum of two test registers the bypass register and the boundary scan register An optional test register has been included with the DS21354 554 design This test register is the identifica...

Page 97: ...O 49 50 TDATA I 48 51 TSYSCLK I 47 52 TSSYNC I 46 53 TCHCLK O 45 54 CO O 44 55 MUX I 43 BUS cntl Note 2 42 56 D0 AD0 I O 41 57 D1 AD1 I O 40 58 D2 AD2 I O 39 59 D3 AD3 I O 60 DVSS 61 DVDD 38 62 D4 AD4...

Page 98: ...ble 17 1 For all bus configurations one SCT will be configured as the master device and the remaining SCTs will be configured as slave devices In the 4 096MHz bus configuration there is one master and...

Page 99: ...18 11 and Figure 18 5 for details 17 2 Frame Interleave In frame interleave mode data is output to the PCM data out bus one frame at a time from each of the connected SCTs This mode is used only when...

Page 100: ...OUTPUT JUST THE SA BITS NOTE 4 RLINK WILL ALWAYS OUTPUT ALL FIVE SA BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM NOTE 5 THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME CHANNEL 32 CHANNE...

Page 101: ...OM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE T1 LINK ETC AND THE F BIT POSITION IS ADDED FORCED TO ON1 NOTE 2 RSYNC IN THE OUTPUT MODE RCR1 5 0 NOTE 3 RSYNC IN THE INPUT MODE RCR1 5 1 NOTE 4 RCHBLK IS...

Page 102: ...NNEL 1 FRAMER 1 CHANNEL 1 3 R SER RSYNC R SIG R SER R SIG FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 1 1 2 2 BIT DETAIL FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2...

Page 103: ...CLK RSYNC FRAMER3 CHANNEL32 MSB LSB FRAMER0 CHANNEL1 R S IG FRAMER3 CHANNEL32 FRAMER0 CHANNEL1 MSB LSB FRAMER0 CHANNEL2 FRAMER0 CHANNEL2 3 R S E R RSYNC R S IG R S E R R S IG 1 1 2 2 BITDETAIL A B C A...

Page 104: ...S BOTH THE CAS MF AND THE CRC4 MF BEGIN WITH THE TAF FRAME NOTE 5 TLINK AND TLCLK ARE NOT SYNCHRONOUS WITH TSSYNC LSB MSB LSB MSB CHANNEL 1 CHANNEL 2 CHANNEL 1 CHANNEL 2 A B C D TCLK TSER TSYNC TSYNC...

Page 105: ...Elastic Store Enabled LSB F MSB LSB MSB CHANNEL 1 CHANNEL 24 TSYSCLK TSER TSSYNC TCHCLK TCHBLK CHANNEL 23 1 2 NOTE 1 THE F BIT POSITION IN THE TSER DATA IS IGNORED NOTE 2 TCHBLK IS PROGRAMMED TO BLOCK...

Page 106: ...1 FRAMER 1 CHANNEL 1 3 TSER TSYNC TSIG TSER TSIG FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 1 1 2 2 BIT DETAIL FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 FR1 CH32...

Page 107: ...LK TSYNC FRAMER 3 CHANNEL 32 MSB LSB FRAMER 0 CHANNEL 1 TSIG FRAMER 3 CHANNEL 32 FRAMER 0 CHANNEL 1 MSB LSB FRAMER 0 CHANNEL 2 FRAMER 0 CHANNEL 2 3 TSER TSYNC TSIG TSER TSIG 1 1 2 2 BIT DETAIL A B C A...

Page 108: ...15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 31 32 TS RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK CHANNEL 26 CHANNEL 25 LSB MSB RCLK RSYSCLK TCLK TSYSCLK RSER TSER RCHCLK TCHCLK RCHBLK TCHBLK 1 2...

Page 109: ...ch FASSA 1 FAS Sync Criteria Met FASSA 0 CAS Sync Criteria Met CASSA 0 If CRC4 is on CCR1 0 1 RLOS 1 If CAS is on CCR1 3 0 Power Up Increment CRC4 Sync Counter CRC4SA 0 CRC4 Resync Criteria Met RIR 2...

Page 110: ...Y TC B R1 2 3 4 R S E R note 1 C C R 3 6 TC R 1 5 S ignalingB it InsertionC ontrol TIRFunctionS elect C C R 3 5 A IS G eneration 0 1 N O TE S 1 TC LKshouldbetiedtoR C LKandTSY N CshouldbetiedtoR FS YN...

Page 111: ...TA 0 C to 70 C for DS21554L VDD 3 3V 5 TA 40 C to 85 C for DS21354LN VDD 5 0V 5 TA 40 C to 85 C for DS21554LN PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 VIH 2 0 5 5 V Logic 0 VIL 0 3 0 8 V Suppl...

Page 112: ...tCYC 200 ns Pulse Width DS Low or RD High PWEL 100 ns Pulse Width DS High or RD Low PWEH 100 ns Input Rise Fall Yimes tR tF 20 ns R W Hold Time tRWH 10 ns R W Setup Time before DS High tRWS 50 ns CS S...

Page 113: ...Intel Bus Read Ac Timing BTS 0 MUX 1 Figure 20 2 Intel Bus Write Timing BTS 0 MUX 1 ASH PW tCYC tASD tASD PW PW EH EL t t t t t t AHL CH CS ASL ASED CS AD0 AD7 DHR tDDR ALE RD WR ASH PW tCYC tASD tASD...

Page 114: ...E1 Single Chip Transceivers 114 of 124 Figure 20 3 Motorola Bus AC Timing BTS 1 MUX 1 tASD ASH PW t t ASL AHL tCS tASL t t t DSW DHW tCH t t t DDR DHR RWH tASED PWEH tRWS AHL PWEL tCYC AS DS AD0 AD7 W...

Page 115: ...1 0 ns Setup Time for CS Active to Either RD WR or DS Active t2 0 ns Delay Time from Either RD or DS Active to Data Valid t3 75 ns Hold Time from Either RD WR or DS Inactive to CS Inactive t4 0 ns Hol...

Page 116: ...re 20 7 Motorola Bus Write AC Timing BTS 1 MUX 0 ADDRESS VALID A0 A7 D0 D7 RD CS WR 0ns MIN 0ns MIN 75ns MIN 0ns MIN 10ns MIN 10ns MIN t1 t2 t6 t4 t7 t8 ADDRESS VALID DATA VALID A0 A7 D0 D7 R W CS DS...

Page 117: ...SCLK Period tSP 100 122 ns 6 tSH 50 ns RSYSCLK Pulse Width tSL 50 ns RSYNC Setup to RSYSCLK Falling tSU 20 tSH 5 ns RSYNC Pulse Width tPW 50 ns RPOSI RNEGI Setup to RCLKI Falling tSU 20 ns RPOSI RNEGI...

Page 118: ...tD2 tD2 tD2 RSER RDATA RSIG RCHCLK RCHBLK RSYNC RLCLK RLINK tD1 Notes 1 RSYNC is in the output mode RCR1 5 0 2 RLCLK will only pulse high during Sa bit locations as defined in RCR2 no relationship bet...

Page 119: ...24 Figure 20 9 Receive System Side AC Timing t F t R tD3 1 tD4 tD4 tD4 t tSU HD 2 RSER RSIG RCHCLK RCHBLK RSYNC RSYNC Notes 1 RSYNCis in theoutput mode RCR1 5 0 2 RSYNCis in theinput mode RCR1 5 1 RSY...

Page 120: ...DS21354 DS21554 3 3V 5V E1 Single Chip Transceivers 120 of 124 Figure 20 10 Receive Line Interface AC Timing t F t R RPOSI RNEGI RCLKI CL t tCP CH t tSU tHD tDD RPOSO RNEGO RCLKO LL t tLP LH t...

Page 121: ...s 3 TSYSCLK Period tSP 100 122 ns 4 tSH 50 ns TSYSCLK Pulse Width tSL 50 ns TSYNC or TSSYNC Setup to TCLK or TSYSCLK Falling tSU 20 tCH 5 or tSH 5 ns TSYNC or TSSYNC Pulse Width tPW 50 ns TSER TSIG TD...

Page 122: ...HD D1 tHD 2 Notes 1 TSYNC is in the output mode TCR1 0 1 2 TSYNC is in the input mode TCR1 0 0 3 TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled 4 TCHCLK a...

Page 123: ...TSYSCLK TSER TCHCLK CO t t SL t SH SP TSSYNC TCHBLK tD3 tD3 t t tSU HD SU tHD Notes 1 TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled 2 TCHCLK and...

Page 124: ...ied Maxim Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600...

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