DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
42 of 124
CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex)
(MSB)
(LSB)
LIUODO CDIG LIUSI
—
— TCLKSRC RESR TESR
SYMBOL
POSITION
NAME AND DESCRIPTION
LIUODO CCR6.7
Line Interface Open-Drain Option.
This control bit determines whether
the TTIP and TRING outputs will be open drain or not. The line driver
outputs can be forced open drain to allow 6Vpeak pulses to be generated
or to allow the creation of a very low power interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
CDIG CCR6.6
Customer Disconnect Indication Generator.
This control bit
determines whether the Line Interface will generate an unframed
...1010... pattern at TTIP and TRING instead of the normal data pattern.
0 = generate normal data at TTIP and TRING as input via TPOSI and
TNEGI
1 = generates a ...1010... pattern at TTIP and TRING
LIUSI CCR6.5
Line Interface G.703 Synchronization Interface Enable.
This control
bit determines whether the line receiver should handle a normal E1 signal
(Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10
of G.703). This control has no affect on the line interface transmitter.
0 = line receiver configured to support a normal E1 signal
1 = line receiver configured to support a synchronization signal
— CCR6.4
Not Assigned.
Should be set to zero when written.
— CCR6.3
Not Assigned.
Should be set to zero when written.
TCLKSRC CCR6.2
Transmit Clock Source Select.
This function allows the user to
internally select RCLK as the clock source for the transmit-side
formatter.
0 = Source of transmit clock determined by CCR2.2 (LOTCMC)
1 = Force transmitter to internally switch to RCLK as source of transmit
clock. Signal at TCLK pin is ignored
RESR CCR6.1
Receive Elastic Store Reset.
Setting this bit from a zero to a one will
force the receive elastic store to a depth of one frame. Receive data is lost
during the reset. Should be toggled after RSYSCLK has been applied and
is stable. Must be cleared and set again for a subsequent reset.
TESR CCR6.0
Transmit Elastic Store Reset.
Setting this bit from a zero to a one will
force the transmit elastic store to a depth of one frame. Transmit data is
lost during the reset. Should be toggled after TSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent reset.
