Cypress MB91460, Manual

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FR, MB91460, FR Clocks
www.cypress.com
Document No. 002-05317 Rev. *C 5
3 Registers
The configuration of the Clock Tree is controlled by the following Registers:
3.1 Clock Source Control Register (CLKR)
Selects the clock source for the base clock used to run the MCU and controls the PLL.
Bit No. Name Explanation Initial
Value
Value Operation
8 - Undefined - Always write 0
3 SCKEN Sub clock select enable 0
0 Stop Sub clock oscillator
1 Enable Sub clock selection
2 PLL1EN Enable Main PLL operation 0
0 Halt Main PLL
1 Enable Main PLL operation
1
CLKS1,
CLKS0
Clock source selection 00
00
Main clock input from X0/X1 divided by
2
01
Main clock input from X0/X1 divided by
2
10 Main PLL
11 Sub clock
3.2 Clock Division Setting Register 0 (DIVR0)
Sets the division ratio for the clocks used for internal device operation.
Bit No. Name Explanation Initial
Value
Value Operation
7-4
B3,B2,
B1,B0
Sets the clock division ratio
for the clock used by the
CPU, internal memory, and
internal buses (CLKB).
0000
0000 Base clock / 1
0001 Base clock / 2
… …
1111 Base clock / 16
3-0
P3,P2,
P1,P0
Sets the clock division ratio
for the clock used by the
peripheral circuits and
peripheral bus (CLKP).
0011
0000 Base clock / 1
0001 Base clock / 2
… …
1111 Base clock / 16
3.3 Clock Division Setting Register 0 (DIVR1)
Sets the division ratio for the clocks used for internal device operation.
Bit No. Name Explanation Initial
Value
Value Operation
7,6,5,4
T3,T2,
T1,T0
Sets the clock division ratio
(relative to the base clock)
for the clock used by the
external bus interface
(CLKT).
0000
0000 Base clock / 1
0001 Base clock / 2
… …
1111 Base clock / 16
3,2,1,0 - Undefined - Always write 0