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FR, MB91460, FR Clocks

www.cypress.com

Document No. 002-05317 Rev. *C

4

Here the BGRn register needs to be configured with the value of 0x0007. So the deviation in the baud rate as per
USART chapter in the hardware manual is 0. But the CLKMOD would also have an impact on this deviation of baud
rate.

Lets also consider that the character format is 8E1 that means one USART character contains 11 bits (1 Start bit + 8
Data bits + 1 Even Parity bit + 1 Stop bit).

If the data that needs to be transmitted is 0x00, the parity bit would also be zero and the USART output should
remain at low level for period of 10 bits. These 10 bits corresponds to the 80 clock periods (cycles) of CLKMOD.

Let’s also consider that the clock modulator is configured for the resolution of 11 and modulation degree of 1 then the
“± phase skew min/max” would be 7.875. This means that the 80 clock periods would be either shortened to 72.125
clock periods or may get lengthened to 87.875 clock period that is the error of up to 1 bit. This may cause parity error
or framing error respectively at the receiver.

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Summary of Contents for MB91460

Page 1: ...ich has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions About Cypress Cypress is the leader in advanced embedded system solutions for the world s most innovative automotive industrial smart home appliances consumer electronics and medical products Cypress microcontrollers analog ICs wireless and USB ...

Page 2: ...ulator Configuration 17 7 Clocks Example 18 7 1 Starting Clock Modulator 18 7 2 Stopping Clock Modulator 18 8 Additional Information 19 Document History 20 1 Introduction The FR Family MCUs feature a sophisticated clock distribution scheme with the different clock sources such as RC Clock Main Clock PLL Clock Modulated PLL Clock and Sub Clock The core and the peripherals are connected to different...

Page 3: ...in Clock is available on all FX devices Main clock 2 is the default clock selected after power on The allowed input frequency is limited to the range 3 5 MHz to 16 MHz when an oscillation circuit is used The range is from 3 5 MHz to 4 MHz when an external clock signal is supplied With respect to EMI considerations a frequency of 4 MHz is recommended 2 4 PLL Clock The PLL Clock is available on all ...

Page 4: ...ated PLL Clock CLKMOD is equal to the reference frequency CLKPLL As a result of the modulation there results in skew in the phase of CLKMOD with reference to CLKPLL This Phase Skew is the maximal phase shift of the CLKMOD relative to the CLKPLL in terms of clock periods of the CLKPLL The phase skew is dependent on configuration such resolution and modulation degrees at a given PLL frequency CLKPLL...

Page 5: ...ty bit 1 Stop bit If the data that needs to be transmitted is 0x00 the parity bit would also be zero and the USART output should remain at low level for period of 10 bits These 10 bits corresponds to the 80 clock periods cycles of CLKMOD Let s also consider that the clock modulator is configured for the resolution of 11 and modulation degree of 1 then the phase skew min max would be 7 875 This mea...

Page 6: ...on Setting Register 0 DIVR0 Sets the division ratio for the clocks used for internal device operation Bit No Name Explanation Initial Value Value Operation 7 4 B3 B2 B1 B0 Sets the clock division ratio for the clock used by the CPU internal memory and internal buses CLKB 0000 0000 Base clock 1 0001 Base clock 2 1111 Base clock 16 3 0 P3 P2 P1 P0 Sets the clock division ratio for the clock used by ...

Page 7: ... Monitor MONCLK inverter 0 0 MONCLK mark level is low 1 MONCLK mark level is high 3 CSC3 Clock Source Selection for LCD Controller 0 0 LCD Controller is sourced by Sub Oscillator 1 LCD Controller is sourced by RC Oscillator 100kHz 2 CSC2 Clock Source Selection for Sub clock calibration 0 0 Sub clock Calibration is sourced by Sub Oscillator 1 Sub clock Calibration is sourced by RC Oscillator 100kHz...

Page 8: ... Sub RUN on CLKRC 0 X 0 Write Does not halt Main clock oscillation during Sub clock mode Read Main clock mode can be selected after the oscillation stabilization time elapses 1 Write Halt Main clock oscillation during Sub clock mode Read Selecting Main clock mode is prohibited 3 6 PLL Control Registers PLLDIVM Bit No Name Explanation Initial Value Value Operation 7 6 5 4 Undefined Always write 0 3...

Page 9: ...tiply by 1 00000001 Divide by G step x 2 multiply by 2 11111111 Divide by G step x 256 multiply by 256 3 10 PLL Control Registers PLLCTRL Bit No Name Explanation Initial Value Value Operation 7 6 5 4 Undefined Always write 0 3 IEDN Interrupt Request Enable Gear DOWN 0 X 0 Gear DOWN interrupt request disabled 1 Gear DOWN interrupt request enabled 2 GRDN Interrupt Flag Gear DOWN 0 X 0 Gear DOWN inte...

Page 10: ...f Sub clock is already missing 1 Perform reset upon transition from Main clock to Sub clock modes if Sub clock is already missing 5 SM Sub clock missing 0 0 Disable Sub clock supervisor 1 Enable Sub clock supervisor 4 RCE RC oscillator enable 1 0 Disable Main clock supervisor 1 Enable Main clock supervisor 3 MSVE Main clock supervisor enable 1 0 Disable RC oscillator 1 Enable RC oscillator 2 SSVE ...

Page 11: ...mode 0 0 Clock frequency un modulated 1 Clock frequency modulated 2 Undefined X Always write 0 1 FMOD Frequency modulation enable bit 0 0 Frequency modulation mode disabled 1 Frequency modulation mode enabled 0 PDX Power down bit 0 0 power down mode 1 power up 3 13 Clock Modulation Parameter Register CMPR The modulation parameter determines the degree of modulation and the maximal and minimal occu...

Page 12: ...tion of Configurations Set the parameter CLOCK_SPEED to CLOCK_USER and the parameters mentioned in chapter 5 1 CLOCKSPEED CLOCK_USER to desired values No clock settings set NO_CLOCK 0x01 Sub oscillation input 32 kHz set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11 Oscillation input 4 MHz set MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ 0x21 set PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_2...

Page 13: ... note if CLOCKSPEED CLOCK_USER set CLOCKSOURCE MAINPLLCLOCK Clock source set ENABLE_SUBCLOCK OFF Sub clock ON OFF set PLLSPEED 0x010F 0x48Ch 0x48Dh PLLDIVM N 64 MHz set DIV_G 0x0F 0x48Eh PLLDIVG set MUL_G 0x0F 0x48Fh PLLMULG Clock Divider set CPUCLOCK 0x00 0x486h DIV0R_B 1 64 MHz set PERCLOCK 0x03 0x486h DIV0R_P 4 16 MHz set EXTBUSCLOCK 0x01 0x487h DIV1R_T 2 32 MHz CAN Clock set PSCLOCKSOURCE PSCL...

Page 14: ...ator feature is not supported by every device e g MB91461 Please check the data sheet Please refer application note AN205200 FR Family MB91460 Series Start91460 asm for further details about using start asm 5 Clock setup sequence First set Clock source Base Clock for the three clock tree selections This selected Base clock is used to select afterwards the 3 Clocks for the different internal trees ...

Page 15: ...1 If interrupts should be received after gearing up or down also enable the corresponding interrupt enables PLLCTRL IEUP PLLCTRL IEDN Wait for the PLL stabilization time Set the base clock division registers DIVR0 DIVR1 Switch the clock source to the PLL CLKR CLKS 00 10 N O Switch the clock source to Main Oscillator If clock was running previously on PLL Gear down PLL Clock Reset Gear down Flag PL...

Page 16: ...f temp 2 PLLDIVG if normal freq switch and auto gear not disabled then wait for gear down while PLLCTRL_GRDN HWWD 0x10 Wait for gear down flag polling HWWD 0x10 Reset gear down flag PLLCTRL_GRDN 0 Switch off the PLL CLKR_PLL1EN 0 Configure Clocks DIVR0 0x00 DIVR0 cpu_clock_div 4 DIVR0 peripheral_clock_div DIVR1 0x00 DIVR1 external_bus_clock_div 4 Set the PLL interface registers N M DG MG PLLDIVM c...

Page 17: ...LL stabilization time 1ms CTBR 0xA5 CTBR 0x5A TBCR 0 TBIF 0 TBIE 0 TBC 000 SYNCR SYNCS 0 TBCR_TBC 2 4 096ms 2MHz while TBCR 0x80 HWWD 0x10 awaiting stabilisation time Switch the clock source to the PLL CLKR_CLKS1 1 Wait for gear UP if counter_g if counter_g 0 auto gear disabled so the flag will not be set while PLLCTRL_GRUP HWWD 0x10 HWWD 0x10 PLLCTRL_GRUP 0 ...

Page 18: ...ck Modulator Parameter Register CMPR register is configured with the appropriate value The MODRUN bit of the CMCR register reflects the status of modulated clock If it is 1 then the CLKMOD can be used as a clock resource for CLKS1 The CMPR register contains modulation parameter which determines the degree of modulation and the maximal and minimal occurring frequencies in the modulated clock Please...

Page 19: ... CLKMOD is 45 18 MHz and max frequency is 51 2 MHz 7 2 Stopping Clock Modulator The following example demonstrates how to stop the clock modulator SAMPLE CODE set PLL clock to 48 MHz CMCR_PDX 1 power up clock modulator for i 0 i 20 i wait for clock modulator s startup time of 6 μs CMPR 0x027F k 1 N 3 c 31 min freq 45 18 MHz max freq 51 2 MHz CMCR_FMOD 1 modulation enable while 1 CMCR_FMOD_RUN wait...

Page 20: ...ress Microcontrollers can be found on the following Internet page http www cypress com cypress microcontrollers The software examples related to this application note is 91460_Clock_Modulator 91460_Clock_Setting It can be found on the following Internet page http www cypress com cypress mcu product softwareexamples ...

Page 21: ...scription of Change NOFL 04 24 2008 V1 0 First draft HPi 05 19 2008 V1 1 Updated Chapter 5 HPi 06 04 2008 V1 2 Updated Chapter 5 HPi A 5090735 NOFL 04 13 2016 Converted Spansion Application Note MCU AN 300066 E V12 to Cypress format B 5869105 AESATMP9 08 31 2017 Updated logo and copyright C 6059091 NOFL 02 05 2018 Updated hyperlinks across the document Updated to new template Completing Sunset Rev...

Page 22: ...fied to make use distribute and import the Software solely for use with Cypress hardware products Any other use reproduction modification translation or compilation of the Software is prohibited TO THE EXTENT PERMITTED BY APPLICABLE LAW CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE INCLUDING BUT NOT LIMITED TO THE IMP...

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