FR, MB91460, FR Clocks
Document No. 002-05317 Rev. *C
14
5.1
Clock Setup Sequence (Example)
Figure 3. Clock Setup Sequence
Switch the clock source to Oscillator (CLKR: CLKS “10”-> “00”), Wait for (PLLCTRL: GRDN) gear down flag (either by
polling or by interrupt). Set the PLL interface registers (PLLDIVN, PLLDIVM, PLLDIVG, and PLLMULG) according to
the selected frequency and gear duration. Switch on the PLL (CLKR: PLL1EN=’1’). If interrupts should be received
after gearing up or down, also enable the corresponding interrupt enables (PLLCTRL: IEUP, PLLCTRL: IEDN). Wait
for the PLL stabilization time. Set the base clock division registers (DIVR0, DIVR1). Switch the clock source to the
PLL (CLKR.CLKS “00”-> “10”)
N
O
Switch the clock source
to Main Oscillator
If clock was running
previously on PLL?
Gear down PLL Clock
Reset Gear down Flag
(
PLLCTRL_GRDN
)
Disable PLL
Set CPU Clock,
Peripheral Clock and
External Bus Clock
Divider
Set PLLDIVM, PLLDIVN,
PLLDIVG and
PLLMULG
Wait for PLL
stabilization time
Switch clock source to
PLL
Wait for Frequency
Gear up
