FR, MB91460, FR Clocks
Document No. 002-05317 Rev. *C
16
/* Disable interrupts */
PLLCTRL_GRDN = 0;
PLLCTRL_GRUP = 0;
/* Switch on the PLL */
CLKR |=0x04;
/* Wait for the PLL stabilization time (>1ms) */
CTBR =0xA5;
CTBR =0x5A;
TBCR = 0;
/* TBIF=0, TBIE=0, TBC=000, SYNCR/SYNCS=0*/
TBCR_TBC = 2;
/* 4.096ms @2MHz */
while
((!(TBCR & 0x80))){
HWWD = 0x10;
/* awaiting stabilisation time */
}
/* Switch the clock source to the PLL */
CLKR_CLKS1 = 1;
/* Wait for gear UP */
if
(counter_g)
{
/*if counter_g == 0; */
/* auto gear disabled so the flag will not be set*/
while ((!PLLCTRL_GRUP)){
HWWD = 0x10;
}
HWWD = 0x10;
}
PLLCTRL_GRUP = 0;
