FR, MB91460, FR Clocks
Document No. 002-05317 Rev. *C
3
2.5
Sub Clock
The Sub Clock is available on all FR dual-clock devices. It can be used as a supplemental clock for low-power
applications. By default, it is enabled, but needs to be selected before use.
The allowed input frequency is limited to the range 32 kHz to 100 kHz when an oscillation circuit is used, while the
range is extended from 0 Hz to 100 kHz when an external clock signal is supplied. Most time-dependent peripherals
offer clock prescalers to allow for full-second intervals when a frequency of 32.768 kHz is provided.
2.6
Clock Modulator
The clock modulator is primarily used to minimize the electromagnetic interference (EMI). It scatters the spectrum of
the clock signal over a wide range of frequencies in order to do so.
The source of the clock for the modulator is the PLL Clock (CLKPLL). The minimum and maximum frequency for a
given reference frequency of CLKPLL and the degree of modulation is dependent on the parameters like resolution of
modulation range and modulation degrees. The average frequency of the resultant Modulated PLL Clock - CLKMOD
is equal to the reference frequency CLKPLL.
As a result of the modulation, there results in skew in the phase of CLKMOD with reference to CLKPLL. This ‘Phase
Skew’ is the maximal phase shift of the CLKMOD relative to the CLKPLL in terms of clock periods of the CLKPLL.
The phase skew is dependent on configuration such resolution and modulation degrees at a given PLL frequency
(CLKPLL).
The following figure explains the phase skew:
Figure 2. Phase Skew
Example:
For CLKPLL of 16 MHz (at a given CMPR configuration), if 100 periods of CLKMOD takes 6.5 microseconds then
phase skew is calculated as follows:
One period of CLKPLL = (1/16 MHz) = 62.5 ns, hence the Phase Skew = (62.5 ns * 100
– 6.5 µs)/ 62.5 ns = -4
periods.
The recommended setting of the modulation parameters (for a given CLKPLL) with the resultant min/max frequency
and phase skew is discussed in greater detail in the hardware manual.
If the USART is used in the asynchronous mode with the clock modulator is switched on, then it would affect the baud
rate of the USART and introduce deviation in the baud rate. In some cases, there may be deviation in the baud rate
which may not be acceptable.
Example:
Let’s consider the case where the required Modulated PLL Clock - CLKMOD is 16 MHz with the desired baud rate for
the USART in asynchronous mode is 2 MBPS.
