Document Number: 002-04578 Rev. *A
Page 15 of 64
MB90910 Series
5. Handling Devices
1.
Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
■
A voltage higher than V
CC
pin or lower than V
SS
pin is applied to an input or output pin.
■
A voltage higher than the rated voltage is applied between V
CC
pin and V
SS
pin.
■
The AV
CC
power supply is applied before the V
CC
voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Use meticulous care not to exceed the rating.
For the same reason, also be careful not to let the analog power-supply voltage (AV
CC
, AVR) exceed the digital power-supply voltage.
2.
Treatment of unused pins
Leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up. Therefore, they must
be pulled up or pulled down through resistors. In this case, those resistors should be more than 2 k
.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.
3.
Using external clock
The high-speed oscillator pins (X0, X1) can not be used for external clock inputs.
4.
Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode
is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Cypress
will not guarantee results of operations if such failure occurs.
