Document Number: 002-04578 Rev. *A
Page 4 of 64
MB90910 Series
1. Product Lineup
(Continued)
Part number
Parameter
MB90V950AMAS
MB90F912BS
MB90911AS
Type
Evaluation product
Flash memory product
MASK ROM product
CPU
F
2
MC-16LX CPU
System clock
On-chip PLL clock multiplier (
1,
2,
3,
4,
6,
8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL
8)
ROM
External
128 Kbytes
64 Kbytes
RAM
30 Kbytes
8 Kbytes
4 Kbytes
Emulator-specific
power supply*
1
Yes
FPGA data*
2
Rev 050617
Adaptor board*
2
MB2147-20 Rev.04C or later
Technology
0.35
m CMOS with built-in power
supply regulator
0.18
m CMOS with built-in power supply regulator
Operation voltage range
5 V
10
3.0 V to 5.5 V : When normal operating
Operating ambient tem-
perature
40 °C to
105 °C
Package
PGA-299
LQFP-48
UART
LIN-UART
7 channels
LIN-UART
2 channels, UART
1 channel
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device (Supported by LIN-UART only)
I
2
C (400 kbps)
2 channels
A/D converter
24 input channels
16 input channels
10-bit or 8-bit resolution
Conversion time : Min 3
s include sample time (per one channel)
16-bit
Reload timer
4 channels
2 channels
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
Machine clock frequency)
Supports External Event Count function
16-bit
I/O timer
2 channels
1 channel
Generates an interrupt signal on overflow
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
, fsys/2
5
, fsys/2
6
, fsys/2
7
(fsys
Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
16-bit
Output compare
8 channels
Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare register
A pair of compare registers can be used to generate an output signal.
