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Ver 2.4
CY3650 USB Development System User’s Guide
6. Switch S3-2 (see Table 2) and Switch S1-5 (see Table 1) will determine the board’s operation mode at
power up reset. Switch S3-2 controls the Run on Reset mode. If enabled the program will begin executing
the program from address 0 following a reset. If disabled the program will be halted at address 0, waiting
for commands from the PC to run, single step, etc. Switch S1-5 controls the Suspend on Power On Reset
mode. If enabled the board goes into suspend mode (see section 5.4) following a Power On Reset. It will
stay suspended until there is a non-idle state on the USB bus input or an interrupt occurs. When this mode
is used the Run on Reset should also be enabled.
Example 2. Program RAM Operation
1. Develop assembly code; assemble and create object code file (see CYASM Assembler User’s Guide; the
object file has a .rom suffix).
2. Set switch S3-1 for program RAM operation.
3. Apply power to the board, and halt microcontroller execution (use the “break” command on the PC debug
software, or have switch S3-2 set to halt operation at power up reset).
4. Download the user object code file to program RAM (refer to the USB Development System Software
Guide).
5. Press the reset switch S2.
6. Switch S3-2 (see Table 2) and Switch S1-5 (see Table 1) will determine the board’s operation mode at
power up reset. Switch S3-2 controls the Run on Reset mode. If enabled the program will begin executing
the program from address 0 following a reset. If disabled the program will be halted at address 0, waiting
for commands from the PC to run, single step, etc. Switch S1-5 controls the Suspend on Power On Reset
mode. If enabled the board goes into suspend mode (see section 5.4) following a Power On Reset. It will
stay suspended until there is a non-idle state on the USB bus input or an interrupt occurs. When this mode
is used the Run on Reset should also be enabled.
Firmware will be held in program RAM until modified via the PC interface, or until power is removed from the
board. Switch S3-1 can be toggled as desired between ROM and RAM operation. In RAM mode, individual bytes
of the program RAM can be modified via the debug software, if desired.
5.3. PC debug interface
Refer to the USB Development System Software Guide for information on operating in the PC debug mode.
5.4. I/O Port operation
On the development board, all I/O port bits (ports P0 to P3) operate identically, and are pseudo-bidirectional. As an
output, each port bit provides a strong pull-down when a ‘0’ is written to the bit. When a ‘1’ is written to the port
bit, it functions as a weak pull-up. The pull-up strength on the board is 10 k
Ω
(components RS4, RS5 for port 0,
RS6, RS7 for port 1). At all times, any read from an I/O port gives the digital value of the voltage on each pin. To
configure any port bit as an input, a ‘1’ must be written to that bit, and the input signal must be able to sink the pull-
up current. The I/O ports may be configured as input only by setting switch S1-4 to the open position.
I/O port operation of the Cypress USB ICs differs from the operation of the development board. In the IC, writing
a ‘0’ to either a port 0/1 output typically puts that bit into Current Sink mode. The value of the output current at
each IC pin depends on settings written to internal control registers (consult the specification for more details). On
the development board the output current is not programmable.
The pull-up disable function on the development board also differs from the ICs. In the IC the Port Pull-Up Regis-
ters can disable the pull-up resistor and select the interrupt polarity for each I/O port bit. On the development board
the interrupt polarity is selected, but to disable the pull-up resistor it must be manually removed from the board.
The port pull-up resistors are resistor packs RS4 through RS11.
