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CY3650

USB Development System

User’s Guide

Version 2.4

June 30, 1999

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Summary of Contents for CY3650

Page 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Page 2: ...CY3650 USB Development System User s Guide Version 2 4 June 30 1999...

Page 3: ...g 1 1 11 20 96 JDW Update switches pin list suspend 1 2 2 0 6 17 97 TEN Modified to incorporate CY7C6341x and CY7C6351x 2 1 7 30 97 TEN Changed J1 odd pins to even and even to odd Expanded explanation...

Page 4: ...Communication 3 3 5 Switch Settings 4 4 Software Installation 5 5 Operation 5 5 1 Differences between the chip and the development board 5 5 2 Firmware ROM vs RAM operation 5 5 3 PC debug interface 6...

Page 5: ...ii Ver2 4 CY3650 USB Development System User s Guide...

Page 6: ...RAM option provides a quick and easy method for testing firmware revisions Stand alone mode Figure 2 allows portable system operation In this case user firmware is loaded in EPROM and only power need...

Page 7: ...ler software Registration Card 3 Hardware Installation This section describes the hardware installation steps necessary for operating the development board These include supplying power to the board c...

Page 8: ...of pin 1 for both J1 and J2 However the printed wiring board shows J1 pin 1 incorrectly Please refer to figure 4 when locating pin numbers 3 4 PC Communication For communicating with a PC plug the enc...

Page 9: ...indow inside you will see tabs select the Advanced tab This sub widow contain the settings for the serial transmit and receive FIFOs Set the receive FIFO to 1 and set the transmit FIFO to 3 if this is...

Page 10: ...ROM is a Cypress CY7C261 45 an 8k x 8 UV erasable EPROM Only 4k of the EPROM is currently addressable The program RAM supports the same memory size as the EPROM To program or erase the EPROM refer to...

Page 11: ...or an interrupt occurs When this mode is used the Run on Reset should also be enabled Firmware will be held in program RAM until modified via the PC interface or until power is removed from the board...

Page 12: ...erates a power on reset When one of these resets occur the following actions take place Program counter is reset to zero Internal registers are reconfigured to their reset state see device specificati...

Page 13: ...interface signals are available at connector J2 Table 4 gives pin functions for the signals and Table 5 lists all signal locations on the J2 connector Consult Figure 4 for the correct position of pin...

Page 14: ...bus DA 7 0 8 bit RAM Address bus MR_ Memory read enable for data RAM active low MW_ Memory write enable for data RAM active low IOW_ I O write enable active low IOR_ I O read enable active low SOI St...

Page 15: ...0 12 IA11 13 IA12 14 GND 15 IRAMS_ 16 IRAMR_ 17 IRAMW_ 18 IOW_ 19 IOR_ 20 SOI 21 22 BRQ 23 IRQ 24 IRA 25 BRA 26 TRQ 27 RESET 28 MASTER RESET 29 MR_ 30 MW_ 31 GND 32 ID0 33 ID1 34 ID2 35 ID3 36 ID4 37...

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