– 4 –
Ver 2.4
CY3650 USB Development System User’s Guide
The required communication settings for the PC are:
It is also recommended that the UART FIFO size settings be set to the minimum values. In Windows 95 the follow-
ing steps will change the FIFO settings:
•
On the desk-top, double click on the “ My Computer” Icon and then double click on the “ Control Panel” Icon. Alter-
nately, use the “start” menu and choose “ Settings” and then “ Control Panel”.
•
In the “ Control Panel” window, double click on the “ System” Icon.
•
In the “ System” window click on the “ Device Manager” tab. Then scroll down through the list of devices to the serial
port used for the USB Development Board, this is usually COM1 or COM2. Select the appropriate device by double
clicking.
•
This brings up a serial device window, inside you will see tabs, select the “ Advanced” tab. This sub-widow contain the
settings for the serial transmit and receive FIFOs. Set the receive FIFO to 1 and set the transmit FIFO to 3 if this is a
valid setting, otherwise set the FIFO size to 1.
3.5. Switch Settings
Two 8-position DIP switches provide configuration options for the two on-board FPGAs. Table 1 and Table 2 list
options for switches S1 and S3 respectively. Further information on these options is given in Section 5. Unused
switches should be left in the default setting, as these may support internal test modes.
Baud Rate
19200
Data Bits
8
Parity
None
Stop Bits
1
Flow Control
None used
Table 1: Switch S1 Configuration
Position
Open (1)
Closed (0)
Function
1
Enable
Disable
USB Bus Reset
2
Enable
Disable
Watch Dog Reset
3
Enable
Disable
Cext (wake up)
4
Enable
Disable
IO Port Input Only Mode
5
Enable
Disable
Suspend on Power On Reset
6
Default
–
Required
7
Default
–
Required
8
Default
–
Required
