CY8C23433, CY8C23533
Document Number: 001-44369 Rev. *B
Page 26 of 37
Figure 9. PLL Lock Timing Diagram
Figure 10. PLL Lock for Low Gain Setting Timing Diagram
Figure 11. External Crystal Oscillator Startup Timing Diagram
Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram
24 MHz
F
PLL
PLL
Enable
T
PLLSLEW
PLL
Gain
0
24 MHz
F
PLL
PLL
Enable
T
PLLSLEWLOW
PLL
Gain
1
32 kHz
F
32K2
32K
Select
T
OS
Jitter24M1
F
24M
Jitter32k
F
32K2
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