Cypress Semiconductor CY8C23433 Specification Sheet Download Page 31

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CY8C23433, CY8C23533

Document Number: 001-44369 Rev. *B

Page 31 of 37

AC Analog Output Buffer Specifications

The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40

≤

C, or 3.0V to 3.6V and -40

≤

C, respectively. Typical parameters apply to 5V and 3.3V at 25

C and

are for design guidance only.

Table 30. 5V AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

ROB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

–
–

2.5
2.5

SOB

Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

–
–

2.2
2.2

ROB

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High

0.65
0.65

–
–

FOB

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High

0.65
0.65

–
–

Small Signal Bandwidth, 20mV

, 3 dB BW, 100 pF Load

Power = Low
Power = High

0.8
0.8

–
–

MHz
MHz

Large Signal Bandwidth, 1V

, 3 dB BW, 100 pF Load

Power = Low
Power = High

300
300

–
–

kHz
kHz

Table 31. 3.3V AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

ROB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

–
–

3.8
3.8

SOB

Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

–
–

2.6
2.6

ROB

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High

0.5
0.5

–
–

FOB

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High

0.5
0.5

–
–

Small Signal Bandwidth, 20mV

, 3 dB BW, 100 pF Load

Power = Low
Power = High

0.7
0.7

–
–

MHz
MHz

Large Signal Bandwidth, 1V

, 3 dB BW, 100 pF Load

Power = Low
Power = High

200
200

–
–

kHz
kHz

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Summary of Contents for CY8C23433

Page 1: ...0 Erase Write Cycles 256 Bytes SRAM Data Storage In System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Sink...

Page 2: ...z for use by the digital system A low power 32 kHz ILO internal low speed oscillator is provided for the Sleep timer and WDT If crystal accuracy is desired the ECO 32 768 kHz external crystal oscillat...

Page 3: ...ion amplifiers 1 with selectable gain to 93x Comparators 1 with 16 selectable thresholds DAC 6 or 9 bit DAC Multiplying DAC 6 or 9 bit DAC High current output drivers two with 30 mA drive 1 3V referen...

Page 4: ...r the PSoC Mixed Signal Array Technical Reference Manual For latest Ordering Packaging and Electrical Specification information refer the latest PSoC device data sheets on the web at http www cypress...

Page 5: ...out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet Once the framework is generated the user can add applicati...

Page 6: ...pheral functions called User Modules User modules make selecting and implementing peripheral devices simple and come in analog digital and mixed signal varieties The standard User Module library conta...

Page 7: ...nt and watch variable features the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values memory locations and exter...

Page 8: ...ion 17 IO P1 6 GPIO 18 Input XRES Active High External Reset with Internal Pull Down 19 IO I P2 0 Direct Switched Capacitor Block Input 20 IO I P2 2 Direct Switched Capacitor Block Input 21 IO P2 4 Ex...

Page 9: ...ed Capacitor Input 21 IO I P2 2 Direct Switched Capacitor Input 22 IO P2 4 External Analog Ground AGnd 23 IO P2 6 Analog Voltage Reference VRef 24 IO I P0 0 Analog Column Mux IP and ADC IP 25 IO I P0...

Page 10: ...device has a total register address space of 512 bytes The register space is referred to as IO space and is divided into two banks The XOI bit in the Flag register CPU_F determines which bank the use...

Page 11: ...1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF DBB00DR0 20 AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24...

Page 12: ...N D1 RW 12 52 92 GDI_O_OU D2 RW 13 53 93 GDI_E_OU D3 RW 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW D6 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB...

Page 13: ...B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FLS_PR1 FA RW 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE 3F 7F BF CPU_SCR0 FF Table 7 Register Map Bank 1 Table Configuration Space conti...

Page 14: ...elsius W micro watts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nano ampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts k kilohm W...

Page 15: ...reliability TA Ambient Temperature with Power Applied 40 85 C Vdd Supply Voltage on Vdd Relative to Vss 0 5 6 0 V VIO DC Input Voltage Vss 0 5 Vdd 0 5 V VIOZ DC Voltage Applied to Tri state Vss 0 5 V...

Page 16: ...3 93 75 kHz analog power off SLIMO mode 0 IMO 24 MHz ISB Sleep Mode Current with POR LVD Sleep Timer and WDT 8 3 6 5 A Conditions are with internal slow speed oscillator Vdd 3 3V 40 C TA 55 C analog p...

Page 17: ...Output Level Vdd 1 0 V IOH 10 mA Vdd 4 75 to 5 25V maximum 40 mA on even port pins for example P0 2 P1 4 maximum 40 mA on odd port pins for example P0 3 P1 5 80 mA maximum combined IOH budget VOL Low...

Page 18: ...apacitance Port 0 Analog Pins 4 5 9 5 pF Package and pin dependent Temp 25 C VCMOA Common Mode Voltage Range Common Mode Voltage Range high power or high opamp bias 0 0 Vdd Vdd 0 5 V The common mode i...

Page 19: ...n includes the limitations imposed by the character istics of the analog output buffer GOLOA Open Loop Gain Power Low Opamp Bias Low Power Medium Opamp Bias Low Power High Opamp Bias Low 60 60 80 dB S...

Page 20: ...d 1 1 0 5 x Vdd 1 1 V V VOLOWOB Low Output Voltage Swing Load 32 ohms to Vdd 2 Power Low Power High 0 5 x Vdd 1 3 0 5 x Vdd 1 3 V V ISOB Supply Current Including Bias Cell No Load Power Low Power High...

Page 21: ...10 1 6 x BG 0 018 V AGND Block to Block Variation AGND Vdd 2 0 034 0 000 0 034 V RefHi Vdd 2 BandGap Vdd 2 BG 0 10 Vdd 2 BG Vdd 2 BG 0 10 V RefHi 3 x BandGap 3 x BG 0 06 3 x BG 3 x BG 0 06 V RefHi 2 x...

Page 22: ...9 P2 4 P2 6 0 057 V RefHi 3 2 x BandGap Not Allowed RefLo Vdd 2 BandGap Not Allowed RefLo BandGap Not Allowed RefLo 2 x BandGap P2 6 P2 6 0 5V Not Allowed RefLo P2 4 BandGap P2 4 Vdd 2 Not Allowed Ref...

Page 23: ...plying Vihp to P1 0 or P1 1 During Programming or Verify 1 5 mA Driving internal pull down resistor VOLV Output Low Voltage During Programming or Verify Vss 0 75 V VOHV Output High Voltage During Prog...

Page 24: ...supply voltage level on Vdd pin VADCVREF Vdd IADCVREF Current when P3 0 is configured as ADC VREF 3 mA INL Integral Non linearity 1 5 1 5 LSB INL limited range Integral Non linearity accommodating a s...

Page 25: ...r 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle FPLL PLL Frequency 23 986 MHz Is a multiple x732 of crystal frequency Jitter24M2 24 MHz Period Jitter PLL 600 ps TPLLSLEW PLL Loc...

Page 26: ...ng Timing Diagram Figure 11 External Crystal Oscillator Startup Timing Diagram Figure 12 24 MHz Period Jitter IMO Timing Diagram Figure 13 32 kHz Period Jitter ECO Timing Diagram 24 MHz FPLL PLL Enabl...

Page 27: ...Strong Mode Cload 50 pF 3 18 ns Vdd 4 5 to 5 25V 10 90 TFallF Fall Time Normal Strong Mode Cload 50 pF 2 18 ns Vdd 4 5 to 5 25V 10 90 TRiseS Rise Time Slow Strong Mode Cload 50 pF 10 27 ns Vdd 3 to 5...

Page 28: ...SOA Falling Settling Time from 20 of V to 0 1 of V 10 pF load Unity Gain Power Low Opamp Bias Low Power Medium Opamp Bias High 5 41 0 72 s s SRROA Rising Slew Rate 20 to 80 10 pF load Unity Gain Power...

Page 29: ...chip 8 1k resistance and the external capacitor Figure 15 Typical AGND Noise with P2 4 Bypass At low frequencies the opamp noise is proportional to 1 f power independent and determined by device geome...

Page 30: ...Vdd 5 25V Maximum Frequency With Capture 24 6 MHz Counter Enable Pulse Width 50 17 ns Maximum Frequency No Enable Input 49 2 MHz 4 75V Vdd 5 25V Maximum Frequency Enable Input 24 6 MHz Dead Band Kill...

Page 31: ...65 V s V s SRFOB Falling Slew Rate 80 to 20 1V Step 100 pF Load Power Low Power High 0 65 0 65 V s V s BWOB Small Signal Bandwidth 20mVpp 3 dB BW 100 pF Load Power Low Power High 0 8 0 8 MHz MHz BWOB...

Page 32: ...fications Symbol Description Min Typ Max Units FOSCEXT Frequency with CPU Clock divide by 1 18 0 093 12 3 MHz FOSCEXT Frequency with CPU Clock divide by 2 or greater 19 0 186 24 6 MHz High Period with...

Page 33: ...es are suppressed by the input filter 0 50 ns Table 37 AC Characteristics of the I2 C SDA and SCL Pins for Vdd 3 0V Fast Mode Not Supported Symbol Description Standard Mode Fast Mode Units Min Max Min...

Page 34: ...w peak temperature and the typical package capacitance on crystal pins Figure 19 32 Pin 5x5 mm QFN 4 DIMENSIONS ARE IN MILLIMETERS 2 BASED ON REF JEDEC MO 248 NOTES 1 HATCH AREA IS SOLDERABLE EXPOSED...

Page 35: ...22 32 QFN 19 4 C W 28 SSOP 95 C W Table 39 Typical Package Capacitance on Crystal Pins Package Package Capacitance 32 QFN 2 0 pF 28 SSOP 2 8 pF Table 40 Solder Reflow Peak Temperature Package Minimum...

Page 36: ...Ordering Code Flash Kbytes RAM Bytes Temperature Range Digital Blocks Rows of 4 Analog Blocks Columns of 3 Digital IO Pins Analog Inputs Analog Outputs XRES Pin 32 Pin QFN CY8C23533 24LQXI 8 256 40 C...

Page 37: ...n translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KI...

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