126
D320 PLC User's Manual
Instruction
Mnemonic
7-Segment Decoder
Range
Bit
■
Word
SEG
Convert the low-order 4 bits of S
into 7-segment display format and
store in D
Double words
Ladder
Convert the value in the low-order 4 bits of address S (0 to 15) into
the proper format for display by a 7-segment display and store in
D. In the converted format, if a bit is 1, the segment is illuminated
(= active high output).
Description
1. Convert the value in the low-order 4 bits of address S into SEG display format, and store it in
D. The high-order 8 bits of D do not change. The 8
th
bit of the D register, used with many 7-
segment display cells as the decimal point, is not affected by this instruction.
For example: S = $XXX5 (hex)
D = $XX6D (hex)
2. This operation will occur on every scan for which the input condition is true (On). To perform
the operation only on a change of input condition, use the rising/falling edge contact.
Example
Program Expression
Operation Results
Initial conditions:
W0 = $876
5
(hex)
W1 = $1234 (hex)
Operation results:
W0 = $8765 (hex)
W1 = $12
6D
(hex)
The 8th bit of W1 does not change.
SEG
D =
S =
R
a
f b
S ... 0 0 0 0 0 1 0 1
D ... 0 1 1 0 1 1 0 1
g f e d c b a
=5
a
f b
g
e c
d
d dp
g
e
c
SEG
D = W1
S = W0
R0.0
R
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