Curtiss-Wright FHB5-PE1MWB04-00 User Manual Download Page 4

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FibreXtreme User Guide

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6 OPERATION

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6.1 Overview

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6.2 Theory of Operation

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6.2.1 Receive Operation

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6.2.2 Transmit Operation

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6.2.3 Loop Operation

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6.3 Data Synchronization

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6.4 Configuration Options

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6.4.1 Flow Control

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6.4.2 Loop Enable

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6.4.3 Receiver/Transmitter Enable

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6.4.4 CRC Generation/Checking

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6.4.5 Stop on Link Error of/SYNC

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7 APPENDIX A

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7.1 Specifications

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7.1.1 SL240 PCIe Specifications

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7.2 Media Interface Specifications

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7.2.1 SL100 PCIe Fibre-Optic Media Interface Specifications

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7.2.2 SL240 PCIe Fibre-Optic Media Interface Specifications

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8 APPENDIX B

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8.1 Overview

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8.2 Ordered Sets Used

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8.3 Frames

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8.3.1 Link Bandwidth

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8.3.2 FPDP Sinnal Sample Rate

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8.4 Data Transmission and Flow Control

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9 APPENDIX C

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9.1 Ordering Information

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9.1.1 SL100/SL240 PCIe Multi-channel Board

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9.1.2 Short Wavelength Multimode Fibre-Optic Cables

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10 APPENDIX D

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10.1 FPDP Information

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10.2 Terminology

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10.3 Parallel FPDP Theory of Operation

Summary of Contents for FHB5-PE1MWB04-00

Page 1: ...Document No F T MU S2PCIENF A 0 A3 SL100 SL240 Multi Channel PCIe User Guide FibreXtreme ...

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Page 3: ...Media 4 5 4 3 Applications 4 5 4 3 1 Typical Digital Signal Processing DSP Imaging System 4 7 4 3 2 Extending FPDP 4 7 4 4 Topologies 4 7 4 4 1 Typical Topologies 4 8 4 4 2 Point to point 4 8 4 4 3 Chained 4 9 4 4 4 Single Master Ring 4 10 4 4 5 Multiple Master Ring 4 10 4 5 Status Link Up LED 1 5 INSTALLATION 5 3 5 1 Overview 5 3 5 2 Unpack the Cards 5 3 5 3 Inspect the Cards 5 3 5 4 Install the ...

Page 4: ... 7 3 7 1 1 SL240 PCIe Specifications 7 4 7 2 Media Interface Specifications 7 4 7 2 1 SL100 PCIe Fibre Optic Media Interface Specifications 7 4 7 2 2 SL240 PCIe Fibre Optic Media Interface Specifications 1 8 APPENDIX B 8 3 8 1 Overview 8 3 8 2 Ordered Sets Used 8 5 8 3 Frames 8 6 8 3 1 Link Bandwidth 8 6 8 3 2 FPDP Sinnal Sample Rate 8 7 8 4 Data Transmission and Flow Control 1 9 APPENDIX C 9 3 9 ...

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Page 7: ...SL100 SL240 1 FOREWORD ...

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Page 9: ...ht This product and all Curtiss Wright LinkXchange products referred to in this document are protected by one or both of the following U S patents 6 751 699 and 5 982 634 CompactFlash is a registered trademark of the Compact Flash Association CFA All Curtiss Wright LinkXchange products referred to in this document are protected by one or both of the following U S patents 6 751 699 and 5 982 634 Cu...

Page 10: ...his product uses and emits electromagnetic radiation which may interfere with other radio and communication devices The user may be in violation of FCC regulations if this device is used in other than the intended market environments CE This information technology product is not compliant with applicable European Union directives for Information Technology equipment ...

Page 11: ...SL100 SL240 2 INTRODUCTION ...

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Page 13: ...ace Definitions of words phrases and terms used in this manual List of key words referenced in this manual The information in this manual is intended for information systems personnel system coordinators or highly skilled network users with at least a systems level understanding of general computer processing memory and hardware operation Style Conventions Called functions are italicized For examp...

Page 14: ...cations ANSI VITA 17 1998 Revision 1 0 February 11 1999 Produced by the VITA Standards Organization IEC 825 1984 Radiation Safety of Laser Products Equipment Classification Requirements and User s Guide 2 parts 1993 FibreXtreme SL100 SL240 Serial FPDP PCIe NSL Software and API Guide Doc No F T ML S2APINSL A 0 LinkXchange GLX4000 Physical Layer Switch Hardware Reference Manual Doc No F T MR L5XL144...

Page 15: ...cedures Improve the quality of our operations to meet the needs of our customers suppliers and other stakeholders Provide our employees with the tools and overall work environment to fulfill maintain and improve product and service quality Ensure our customer and other stakeholders that only the highest quality product or service will be delivered The British Standards Institution BSI the world s ...

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Page 17: ...SL100 SL240 3 TECHNICAL SUPPORT ...

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Page 19: ...you may have specific problems or issues this document does not satisfactorily cover Our goal is to offer a combination of products and services that provide complete easy to use solutions for your application If you have any technical or non technical questions or comments contact us Hours of operation are from 8 00 a m to 5 00 p m Eastern Standard Daylight Time Phone 937 252 5601 or 800 252 5601...

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Page 21: ...SL100 SL240 4 PRODUCT OVERVIEW ...

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Page 23: ...erformance so for example combining two lanes will yield 10 Gbps throughput The SL240 PCIe is an 8 lane x8 board with a maximum of 1 Gigabyte per second of throughput per transmit and receive directions It incorporates many of the advanced protocol features in PCI Express such as Automatic Lane Reversal The SL240 PCIe can interoperate with Curtiss Wright s existing FibreXtreme family of products T...

Page 24: ...and are removable The major SL240 PCIe features are listed below x8 Link Full duplex PCI Express lanes 5 Gbps each Automatic lane reversal 8b 10b encoding Link training auto negotiate to smallest link width 256 byte maximum payload size End to end CRC and data poisoning Advanced error reporting Link management Advanced flow control Turn off unused lanes for power reduction Additional SL240 PCIe Fe...

Page 25: ...ls Inc Technical Support Figure 5 1 4 3 Applications SL240 PCIe cards are used in a variety of topologies for a variety of applications The following sections detail typical topologies used and some applications Many other applications are possible in these configurations The SL240 s applications can be further expanded with the use of additional Curtiss Wright equipment whose features are also co...

Page 27: ...e type of transceiver used determines the distance the FPDP cards can be separated See section 2 2 1 Media Options for details on transceivers Using fiber optics provides electrical isolation Figure 2 3 FibreXtreme SL240 PCIe Extending FPDP 4 4 Topologies 4 4 1 Typical Topologies There are four typical topologies for the SL240 PCIe card These topologies should cover most customer applications if a...

Page 28: ...same time The maximum distance between the nodes is 26 km There are many applications for the point to point topology as long as it involves only two nodes this topology covers it One advantage that point to point has over the other topologies is the ability to do simultaneous bi directional traffic Figure 2 4 Point to Point Topology 4 4 3 Chained This topology is a single transmitter on the end o...

Page 29: ...oid bringing down the loop A switch suitable for this purpose is the LinkXchange GLX4000 Physical Layer Switch available from Curtiss Wright Software controls mastership switching of the ring There are rules associated with master switching listed in the Programming Interface section The flow control used in this case is similar to a multi drop FPDP bus where any receiver can back the transmitter ...

Page 30: ... rings above two nodes and the data cannot be passed through masters unless control guarantees that there is at least one source only node on the ring and that no two masters will transmit at the same time Single master rings should temporarily become multiple master rings when switching loop masters Figure 2 7 Multiple Master Ring 4 5 Status Link Up LED The Link Up LEDs indicate a signal is prese...

Page 31: ...SL100 SL240 5 INSTALLATION ...

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Page 33: ...the card Follow the steps below to unpack the card 1 Put on the wristband attached to an anti static mat 2 Remove the card and anti static bag from the carton 3 Place the bag on the anti static mat 4 Open the anti static bag and remove the card 5 In the unlikely event that you should need to return your SL240 PCIe card please keep the original shipping materials for this purpose Any optional equip...

Page 34: ...8 X16 or x32 PCIe slot on the motherboard as shown in Figure 5 1 step 1 and 2 until it is firmly seated Install the mounting screw as shown in step 3 NOTE The SL240 PCIe requires an x8 PCIe bus slot for proper operation The board cannot be installed in an x4 x2 or x1 PCIe bus slot Figure 5 2 SL240 PCIe Card Installation ...

Page 35: ... into the transmitter receiver connector it may not be possible to clean the connector out and could result in damage to the transmitter or receiver lens Hair dirt and dust can interfere with the light signal transmission Use an alcohol based wipe to clean the cable ends For short wavelength laser modules either a 50 µm or 62 5 µm core diameter cable should be used For distances up to 300 meters 6...

Page 36: ...nce Please be prepared to supply the following information Machine __________________________________________ OS Name __________________________________________ OS Version __________________________________________ Card Type __________________________________________ Card Serial __________________________________________ Software Part __________________________________________ Software S N _______...

Page 37: ...SL100 SL240 6 OPERATION ...

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Page 39: ... a set of useful features with which to customize your applications The hardware offers many different features for advanced applications while maintaining a simple interface to the most commonly used features NOTE For further explanation of terms used in this chapter refer to the FPDP Primer in Appendix D 6 2 1 Receive Operation The SL240 PCIe has several options for receiving data The most basic...

Page 40: ...damental difference between a loop master and a receiving node is the loop master does not have its loop retransmission enabled Therefore to the loop master it appears as if it is still in a point to point connection with a single node Receiving nodes on the other hand have knowledge that they are in a loop configuration and must be configured as such Note that the loop master receives all the dat...

Page 41: ...on 6 4 Configuration Options The data synchronization primitive SYNC is sent across the link under user control This primitive synchronizes with the data stream and is written to the transmit FIFO under user control or through the transaction channels The SYNC may correspond to SYNC without DVALID or SYNC with DVALID on the FPDP interface depending on the card s configuration Unless a non intellig...

Page 42: ...ration Checking option allows the SL240 card to detect data transmission errors The card is not capable of correcting the errors Error correction is left to application level design A single bit controls both generation and checking CRC should be used in almost all applications It offers excellent coverage of data errors and has very little impact on link throughput for maximum frame sizes The opt...

Page 43: ...SL100 SL240 7 APPENDIX A ...

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Page 45: ...7 mm 6 87 inches x 4 173 inches Weight 0 25 lbs Operating Voltage 12 volt supply 11 75 Volts to 12 25 V Power Dissipation 12 Volt Supply 21 6 Watts Peak 12 V Electrical Requirements 12 Volt Supply 1 8 Amps Peak Temperature Requirements Storage 40 to 85 C Operation 0 to 50 C with 200 LFM air minimum Humidity Range Storage 0 to 95 noncondensing Operating 10 to 90 noncondensing Maximum Node Separatio...

Page 46: ...m Fiber Length 550 m with 50 µm fiber 300 m with 62 5 µm fiber Transmit Wavelength 830 to 860 nm Transmit Power 10 to 4 dBm Receive Wavelength 770 to 860 nm Receive Sensitivity 16 to 0 dBm 7 2 2 SL240 PCIe Fibre Optic Media Interface Specifications Connector Duplex LC 850 nm Media 50 µm or 62 5 µm multimode fiber Maximum Fiber Length 250 m with 50 µm fiber 125 m with 62 5 µm fiber Transmit Wavelen...

Page 47: ...SL100 SL240 8 APPENDIX B ...

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Page 49: ...l denotes a certain mapping of the transmission words in the 8B 10B protocol to be ordered sets which denote special control information for Fibre Channel These same ordered sets are used in VITA 17 1 but are assigned different meaning There are eighteen ordered sets used by SL240 PCIe to denote different information Twelve of these ordered sets are used to embed five bits of data eight start of f...

Page 50: ...R 1 SOFn3 SOF Start of Frame PIO1 1 PIO2 1 DIR 0 SOFf SOF Start of Frame PIO1 1 PIO2 1 DIR 1 EOFt SEOF Status EOF FIFO Overflow 0 NRDY 0 EOFdt SEOF Status EOF FIFO Overflow 0 NRDY 1 EOFa SEOF Status EOF FIFO Overflow 1 NRDY 0 EOFn SEOF Status EOF FIFO Overflow 1 NRDY 1 EOFni MEOF Mark EOF EOF for a SYNC frame EOFdti FEOF Frame EOF EOF for a normal data frame R_RDY SWDV SYNC with DATA Valid Says th...

Page 51: ...IDLEs to maintain synchronization SYNC is used to delimit data streams and maintain host program synchronization This signal is under user control for PCI based products and is the same as the FPDP SYNC signal for CMC FPDP based products Whenever a SYNC appears on the output of the Transmit FIFO the current frame is terminated and the proper SYNC frame SYNC with data or SYNC without data is sent F...

Page 52: ... and Copy Mode Master bit 1 Without CRC and Copy Mode Master bit 1 SL240 247 10 MB s 247 58 MB s 245 68 MB s 246 15 MB s NOTE The Copy Master Mode is located in the Link Control register 8 3 2 FPDP Sinnal Sample Rate The states of the FPDP signals PIO1 PIO2 DIR and NRDY are transmitted across the link at varying rates The worst case rate at which these signals are sampled is for CRC checked filled...

Page 53: ...then the data waits in the Transmit FIFO until the signal changes Curtiss Wright SL240 PCIe cards use the same protocol when transmitting from either end to allow the link to operate bi directionally Since these data streams are independent the maximum throughput on the link would be 494 MB s 247 MB s direction for SL240 The receiver should transmit the STOP signal when it has space for the data c...

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Page 55: ...SL100 SL240 9 APPENDIX C ...

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Page 57: ...d Table 7 1 SL100 SL240 PCIe Multi channel Order Number Description FHB5 PE1MWB04 00 SL100 PCIe x8 form factor with one SFP optical transceiver FHB5 PE2MWB04 00 SL100 PCIe x8 form factor with two SFP optical transceivers FHB5 PE4MWB04 00 SL100 PCIe x8 form factor with four SFP optical transceivers FHB7 PE1MWB04 00 SL240 PCIe x8 form factor with one SFP optical transceiver FHB7 PE2MWB04 00 SL240 PC...

Page 58: ...xxxx 00 Custom LC LC Table 7 3 LC to ST Simplex Part Number Duplex Part Number Length Cable End 1 Cable End 2 FHAC M1LCST03 00 FHAC M2LCST03 00 3 meters LC ST FHAC M1LCST05 00 FHAC M2LCST05 00 5 meters LC ST FHAC M1LCST10 00 FHAC M2LCST10 00 10 meters LC ST FHAC M1LCST20 00 FHAC M2LCST20 00 20 meters LC ST FHAC M1LCST30 00 FHAC M2LCST30 00 30 meters LC ST FHAC M1LCSTxx 00 FHAC M2LCSTxx 00 Custom L...

Page 59: ...SL100 SL240 10 APPENDIX D ...

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Page 61: ...provide the required bandwidth and latency at all times because of bus contention The primary bus must also handle other tasks such as system control The FPDP bus provides a solution to this problem Using FPDP two or more cards are connected by a simple parallel synchronous interface using 80 conductor ribbon cable running across the cards front panels or through a 2 5 Gbps serial interface For pa...

Page 63: ...ta rate Some additional advantages of Serial FPDP are Noise immune fiber optic interface Significantly increased transmission distance 10 km Standard cards for parallel FPDP custom backplanes PCI PCI PMC and others available 10 2 Terminology Some FPDP specific terms are defined below FPDP TRANSMIT MASTER FPDP TM An FPDP TM is a device that transmits data and timing signals onto the FPDP bus This d...

Page 64: ...the number of data items in the frame Unframed data may also be transmitted onto the FPDP bus The four data frame types defined by the FPDP specification are listed and described below Unframed data Single frame data Fixed size repeating frame data Dynamic size repeating frame data UNFRAMED DATA Used when the source and the organization of the data is not important Used when the FPDP receivers do ...

Page 65: ...data frames are the same size when fixed size repeating frame data is transmitted DYNAMIC SIZE REPEATING FRAME DATA Synchronization must occur prior to data to which it applies Synchronization occurs at the same time the last data word in the block before is transferred SYNC must be asserted at the end of the data block while DVALID is still asserted Because synchronization occurs at the end of th...

Page 66: ...RM and FPDP R devices The FPDP RM and FPDP R devices must assert NRDY when they are not ready to accept data and must de assert NRDY otherwise The NRDY signal is asynchronous to the STROBE clock and should be double synchronized by the FPDP TM before being used in order to avoid metastability problems As required by the Front Panel Data Port Specifications ANSI VITA 17 1998 the FPDP TM transmits t...

Page 68: ...pyright 2017 Figure 8 3 FPDP Timing Diagrams Showing the Use of Framing The timing parameters from Figure 8 2 and D 3 are detailed in Table 8 1 and D 2 These timing specifications are taken from Front Panel Data Port Specifications ANSI VITA 17 ...

Page 69: ...a DVALID SYNC setup time 6 0 ns min 5 0 ns min TTL 1 Data DVALID SYNC setup time 5 5 ns min 4 5 ns min PECL 2 Data DVALID SYNC hold time 12 8 ns min 11 8 ns min TTL 2 Data DVALID SYNC hold time 12 0 ns min 11 0 ns min PECL Table 8 2 FPDP Transmitter Interface Timing Specifications Parameter Description Min Max 3 SUSPEND asserted to data stop 16 clocks 4 SUSPEND de asserted to data started 1 clock ...

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Page 71: ...5 5 5 5 CRC 6 4 6 6 D damaged 5 3 DIR 6 3 distance 4 8 distances 5 5 DMA 6 3 6 6 DSP 4 5 DVALID 6 5 E efficiency 8 6 encoding 4 4 EOF 8 3 F fiber optic 5 3 FIFO 4 9 6 3 flow control 4 8 FPDP 4 4 4 7 4 9 frames 8 5 H HBA 4 4 host 4 4 6 3 L lane 8 3 Lane Reversal 4 3 lanes 4 3 4 4 laser modules 5 5 latency 4 4 6 3 LC 4 5 link 4 4 4 7 6 3 M master 4 9 MIL HDBK 217 7 3 motherboard 5 3 MTBF 7 3 multi d...

Page 72: ...Ie 4 3 4 5 PIO 6 3 PIO1 6 3 R receivers 5 5 rings 4 10 S scalable 4 3 4 4 SEOF 8 3 SFP 4 4 slot 5 3 Small Form 4 4 SOF 6 4 STOP 6 4 strobe 10 6 Style Conventions 2 2 3 SUSPEND 6 3 SWDV 6 4 SYNC 6 3 T throughput 4 3 6 3 Transceiver 4 4 V video 4 8 VITA 17 1 8 3 W Wavelength 5 5 5 5 7 4 ...

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