Curtiss-Wright FHB5-PE1MWB04-00, User Manual, Page: 39 / 72

OPERATION
6-3
FibreXtreme User Guide Copyright 2017
6.1 Overview
SL240 PCIe cards move data with very low latency between a host interface and a 5 Gbps link.
The SL100 PCIe version uses 1G SFP optical transceivers and operates in environments where a
lower system throughput is acceptable. Both cards must be installed in an x8, x16, or x32 PCIe
bus slot.
NOTE : It is not possible for SL100 and SL240 PCIe cards to communicate with one
another on the link because the link speeds are not compatible.
CAUTION : Do not break the link between two SL240 PCIe cards. The unpredictable
results may affect your system. While the FPGA can recover from link break scenarios, the
corresponding link and data errors caused by disruption of the link must be adequately
addressed by the host interface.
6.2 Theory of Operation
The operation of SL240 PCIe cards is simple—take data from the host bus interface and transmit
it across a link, or take data from the link and pass it to the host bus interface. The link protocol
involved is kept minimal to reduce the latency and improve throughput, while still providing a set
of useful features with which to customize your applications. The hardware offers many different
features for advanced applications, while maintaining a simple interface to the most commonly
used features.
NOTE: For further explanation of terms used in this chapter, refer to the FPDP Primer in
Appendix D.
6.2.1 Receive Operation
The SL240 PCIe has several options for receiving data. The most basic option is no-loop
operation with data-receive enabled. In this case, data is:
1. Received from the link.
2. Decoded by the card.
3. Placed in the receive FIFO.
If a receive DMA is started, the data is automatically moved into the PCIe address given by the
DMA transaction. If a DMA is not started, the data waits in the receive FIFO until the host either
PIOs the data out or sets up the DMA transaction to remove it.
FPDP signals are embedded into the control words of a frame. The FPDP signals transported
across are: /NRDY, /DIR, /SYNC, PIO1 and PIO2. A /SUSPEND signal is synthesized by the
transmit state machine in response to how full the receive FIFO is—this is not the /SUSPEND
from an FPDP port.
All FPDP signals, with the exclusion of /SYNC, are passed around the receive FIFO, and are not
synchronized with the data stream. The FPDP signals can be read from a register once they are
received from the link.