Curtiss-Wright FHB5-PE1MWB04-00, User Manual

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APPENDIX B
8-3
FibreXtreme User Guide Copyright 2017
8.1 Overview
NOTE : The FibreXtreme SL100 and SL240 PCIe Cards will be referred to throughout this
appendix as SL240 PCIe. Anything that is exclusive to the SL100 PCIe Cards will be
described as such.
The SL240 PCIe Serial FPDP protocol (also known as VITA 17.1) is designed to provide near
optimal throughput while maintaining low overhead. The link transfer rate for the SL240 PCIe
card is 5 Gbps per lane. Since an 8B/10B encoding scheme is used, this corresponds to a raw
data rate of 1000 MBps (1 GBps) for the SL240. Based on the protocol presented here, the
usable throughput of each link available to the user is 247 MBps for the SL240. All ordered sets
used by this protocol are standard Fibre Channel ordered sets with the exception of positive
IDLE, which is allowed for a more flexible receiver interface
NOTE : The protocol referred to throughout this document is the protocol used by the
transmitter and accepted by the receiver. The receiver does not have to see the protocol
defined here to receive data. Any generic Fibre Channel data stream with an IDLE at least
every 4096 words can be used.
8.2 Ordered Sets Used
Fibre Channel denotes a certain mapping of the transmission words in the 8B/10B protocol to be
ordered sets, which denote special control information for Fibre Channel. These same ordered
sets are used in
VITA 17.1 , but are assigned different meaning.
There are eighteen ordered sets used by SL240 PCIe to denote different information. Twelve of
these ordered sets are used to embed five bits of data—eight start-of-frame (SOF) sets are used
to embed three bits at the start of a frame, and four status-end-of-frame (SEOF) sets are used to
embed two bits at the end of the frame. The SOF ordered sets embed three FPDP signals -
PIO1, PIO2, and DIR.
Note that although the direction signal on FPDP is active low (/DIR), the signal transmitted on the
link is active high (DIR).
The four EOF ordered sets embed the FPDP signal NRDY (once again, the inverted version of
the FPDP interface’s /NRDY) and Transmit FIFO Overflow flag.
There are two additional EOF ordered sets used by SL240 PCIe to denote the actual end of
frame. The Mark EOF (MEOF) denotes a frame that has SYNC associated with it, and the
Frame EOF (FEOF) denotes a normal data frame. The other four ordered sets are inter-frame
padding used to denote flow control information and alternate frame interpretations. Table 6-1
shows the mappings from the Fibre Channel ordered sets onto the VITA 17.1 ordered sets, along
with the meaning associated with each ordered set.