6-16 Memory Configuration and BIOS Settings
Passive Release
If this is enabled, the chipset will provide a programmable passive
release mechanism to meet the required ISA master latencies.
Delayed
Transaction
Since PCI specification version 2.1 requires much tighter controls on
target and master latency, PCI cycles to or from ISA typically take
longer. If this item is enabled, the chipset will provide a
programmable delayed completion mechanism to meet the required
target latencies.
AGP Aperture Size
(MB)
Specifies the maximum amount, in MB, of system memory an AGP
display card can use to store 3D texture mapping data. The larger the
aperture, the better the performance of the card’s 3D function. The
settings range from 4 MB to 256 MB.
SDRAM RAS-to-
CAS Delay
When SDRAM is refreshed, both rows and columns are addressed
separately. This item allows you to specify the timing of the transition
from Row Address Strobe (RAS) to Column Address Strobe (CAS).
The setting can be Slow for 3 CLKs or Fast for 2 CLKs.
SDRAM RAS
Precharge Time
SDRAM must continually be refreshed or it will lose its data.
Normally, DRAM is refreshed entirely as the result of a single
request. This item allows you to specify the number of CPU clocks
allocated for Row Address Strobe to accumulate its charge before the
DRAM is refreshed. If the amount of time specified is insufficient,
DRAM refresh may be incomplete and data may be lost. The setting
can be Slow for 3 CLKs or Fast for 2 CLKs.
SDRAM CAS
Latency Time
Defines the CAS Latency timing parameter of the SDRAM, expressed
in 66 MHz clocks. The setting can be 2 CLKs or 3 CLKs.
Table 6-6: The Chipset Features Setup Screen items.
Item
Description