6-14 Memory Configuration and BIOS Settings
EDO RAS# to
CAS# Delay
When EDO DRAM is refreshed, both rows and columns are
addressed separately. This item allows you to determine the timing of
the transition from Row Address Strobe (RAS) to Column Address
Strobe (CAS). The setting can be 3 or 2.
EDO RAS#
Precharge Time
Sets the DRAM RAS Precharge Timing.
DRAM must continually be refreshed or it will lose its data.
Normally, DRAM is refreshed entirely as the result of a single
request. This item allows you to specify the number of CPU clocks
allocated for Row Address Strobe to accumulate its charge before the
DRAM is refreshed. If amount of time specified is insufficient,
DRAM refresh may be incomplete and data may be lost. The setting
can be 4 CLKs or 3 CLKs.
EDO DRAM Read
Burst
Sets the EDO DRAM Read Burst Timing.
The timing used depends on the type of DRAM chip (EDO Burst
mode or Standard Fast Page mode) inserted into each DIMM (Dual
Inline Memory Module) socket. The setting can be x222 or x333.
EDO DRAM
Write Burst
Sets the EDO DRAM Write Burst timing for accessing DRAM. The
setting can be x222 or x333.
DRAM Data
Integrity Mode
Allows the user to set DRAM Data Integrity mode to ECC (Error
Checking and Correcting) or Non-ECC. The ECC setting allows
detection of single-bit and multiple-bit errors, and recovery of single-
bit errors. The Non-ECC setting enables byte-wide write capability
but has no provision for protecting data integrity in the DRAM array.
Table 6-6: The Chipset Features Setup Screen items.
Item
Description
