CNT24-4(PCI)
I/O Ports and Registers
47
External
input signal
Digital
Filter
PC
input signal
in valid
4 clock of the sampling frequency
External
input signal
PC
input signal
valid
Figure 4.11. Digital Filter
Table 4.6. Digital Filter Clock Data
D3
D2
D1
D0
Clock frequency
Input frequency numbers
0
0
0
0
0.1
µ
sec
about under 1MHz
0
0
0
1
6.5
µ
sec
15
0
0
1
0
25.7
µ
sec
3.5
0
0
1
1
32.1
µ
sec
3
0
1
0
0
204.9
µ
sec
480Hz
0
1
0
1
211.3
µ
sec
470Hz
0
1
1
0
230.5
µ
sec
430
0
1
1
1
236.9
µ
sec
420
1
0
0
0
819.3
µ
sec
122
1
0
0
1
825.7
µ
sec
121
1
0
1
0
844.9
µ
sec
118
1
0
1
1
851.3
µ
sec
117
1
1
0
0
1024.1
µ
sec
97
1
1
0
1
1030.5
µ
sec
96
1
1
1
0
1049.7
µ
sec
95
1
1
1
1
1056.1
µ
sec
94
* The accuracy is 0.01% of the setting frequency.
Notes!
- The default is 100nsec setting.
- Some noise causes more than a four clock delay of the set
frequency.
- If the level changes faster than the sampling clock frequency that
has been set, the level change is invalid and there is no count.
Latch count.