I/O Ports and Registers
CNT24-4(PCI)
38
The counter is zero-cleared when one Z-phase input is enabled;
this bit changes to 0 (RESET=0) and one Z-phase input is again
enabled.
SEL
:
Switches the pulse input for the counter.
0 : Photocoupler insulation input
1 : TTL level input
ZSEL :
Selects logic for Z-phase input
0 : Positive logic (HIGH active)
1 : Negative logic (LOW active)
UD/AB, SEL2-SEL0 :
Set the counter operation mode
Table 4.3. Counter Operation Mode
UD/AB
DIR
SEL2
SEL1
SEL0
Operation mode
2-phase input, Synchronization clear,
Single multiplication mode
2-phase input, Synchronization clear,
Double multiplication mode
2-phase input, Synchronization clear,
Quadruple multiplication mode
2-phase input, Asynchronization clear,
Single multiplication mode
See
2-phase input, Asynchronization clear,
Table4.4.
Double multiplication mode
2-phase input, Asynchronization clear,
Single multiplication mode
Single-phase input, Asynchronization clear,
Quadruple multiplication mode
Single-phase input with gate control,
Asynchronization clear, Double multiplication mode
Single-phase input with gate control,
Asynchronization clear, Double multiplication mode
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
0
1
1
1