6. About Hardware
AD12-8(PM)
73
Control Signal Timings
t
SFS
t
HFS
t
DEC
External Sampling Clock Input
Conversion Start
Figure 6.2. Timing Chart of External Sampling Clock
Table 6.2. Control Signal Timings
Parameter Symbol
Time
(nsec)
Setup time for falling edge of external sampling clock signal
t
DEH
100
Hold time for falling edge of external sampling clock signal
t
DEC
100
Delay from falling edge on external sampling clock signal until AD conversion
starts on first channel
t
SRS
100
CAUTION
The times listed in Table 6.2 are for standard operating conditions.
