Copyright
©
2013
congatec
AG
QMX6m03
45/63
9.1
PCI Express™
Table 6 PCI Express Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
Comment
P
PCIE0_RX-
180
182
PCI Express channel 0, Receive Input differential pair.
I PCIE
Supports PCI Express Base Specification, Revision 1.0a.
P
PCIE0_TX-
179
181
PCI Express channel 0, Transmit Output differential pair. O PCIE
Supports PCI Express Base Specification, Revision 1.0a.
P
PCIE1_RX-
174
176
PCI Express channel 1, Receive Input differential pair.
I PCIE
Not supported.
P
PCIE1_TX-
173
175
PCI Express channel 1, Transmit Output differential pair. O PCIE
Not supported.
P
PCIE2_RX-
168
170
PCI Express channel 2, Receive Input differential pair.
I PCIE
Not supported.
P
PCIE2_TX-
167
169
PCI Express channel 2, Transmit Output differential pair. O PCIE
Not supported.
P
PCIE3_RX-
162
164
PCI Express channel 3, Receive Input differential pair.
I PCIE
Not supported.
P
PCIE3_TX-
161
163
PCI Express channel 3, Transmit Output differential pair. O PCIE
Not supported.
PCIE_
PCIE_CLK_REF-
155
157
PCI Express Reference Clock Signals for Lanes 0 to 3.
O PCIE
PCIE_WAKE#
156
PCI Express Wake Event: Sideband wake signal
asserted by components requesting wakeup.
I 3.3VSB PU 1k 3.3VSB connected to GPIO
PCIE_RST#
158
Reset Signal for external devices.
O 3.3V
9.2
UART
Table 7 UART Signal Descriptions
Signal
Pin #
Description
I/O
PU/PD
Comment
UART0_TX
171
Serial Data Transmitter
O 3.3V
UART3_TX signal from Processor
UART0_RX
177
Serial Data Reciever
I 3.3V
UART3_RX signal from Processor
UART0_CTS#
178
Handshake signal, ready to send data
I 3.3V
UART3_CTS# signal from Processor
UART0_RTS#
172
Handshake signal, ready to receive data
O 3.3V
UART3_RTS# signal from Processor