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2013
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QMX6m03
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5.17
I2C Bus
The I2C bus is suitable for applications requiring occasional communications over a short distance between many devices. The I2C interfaces
offered by the Freescale
®
i.MX6 processor support up to 400 kbps, depending on pin loading and timing characteristics
The conga-QMX6 offers three I2C interfaces (I2C1, I2C2 and I2C3) on the Qseven edge connector. The I2C2 and I2C3 buses on the edge
connector are shared with some onboard devices - I2C3 is shared with LVDS and RTC while I2C2 is shared with camera interface and HDMI.
The I2C1 bus is routed directly without sharing on the edge connector.
Note
On the conga-QMX6 revision B.x and later, we implemented a multiplexer on the I2C2 interface. The multiplexer separates the PMIC functions
from other devices (camera, HDMI) that share the bus. Due to this implementation, the user needs to download the latest kernel from
git.congatec.com/public or at least ensure the congatec I2C multiplexer patches (CGT000031, CGT000032) are applied to the desired kernel,
to achieve proper behaviour.
The I2C3 is also available on the SMB Bus signals (pin 60 and 62) of the Qseven edge connector.
