Cirrus Logic CS4399, Manual

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DS1113F1 33
CS4399
4.6 Clock Output and Fractional-N PLL
Table 4-4 lists common settings with XTAL input as PLL reference.
Table 4-5 lists common settings with MCLK input as PLL reference.
Note that in Table 4-4 and Table 4-5 :
• The PLL_OUT_DIV value must be even.
• PLL_OUT frequencies are at 22.5792 or 24.576 MHz. CLKOUT frequencies can be obtained by configuring the
CLKOUT_DIV value:
• PLL_ERROR_INT constantly monitors the PLL error status after PLL_START is set, assuming the PLL reference
input is stable and accurate.
4.6.2.1 Powering Up the PLLs
To power up the PLL, follow the following default sequence:
1. Enable the PLL by clearing PDN_PLL.
2. Configure PLL_REF_PREDIV.
3. Configure PLL_OUT_DIV.
4. Configure the three fractional factor registers, PLL_DIV_FRAC.
5. Set the integer factor, PLL_DIV_INT, to the desired value.
6. Configure PLL_MODE and PLL_CAL_RATIO.
Table 4-4. PLL Configuration for Typical Use Case (XTAL as the PLL Reference)
XTAL
(MHz)
PLL_REF_PREDIV
(Divide-by Value)
PLL_REF_PREDIV
(Setting)
PLL_
DIV_INT
PLL_DIV_FRAC PLL_OUT_DIV
PLL_
MODE
PLL
OUT
(MHz)
PLL_CAL_
RATIO
22.5792 8 0x3 0x44 0x06 F700 0x08 0 24.576 139
24.576 8 0x3 0x49 0x80 0000 0x0A 1 22.5792 118
Table 4-5. PLL Configuration for Typical Use Case (XIN/MCLK as the PLL Reference)
XIN/MCLK
(MHz)
PLL_REF_PREDIV
(Divide-by Value)
PLL_REF_PREDIV
(Setting)
PLL_DIV_INT PLL_DIV_FRAC PLL_OUT_DIV
PLL_
MODE
PLL_OUT
(MHz)
PLL_CAL_
RATIO
11.2896 4 0x2 0x40 0x00 0000 0x08 1 22.5792 128
4 0x2 0x44 0x06 F700 0x08 0 24.576 139
22.5792 8 0x3 0x44 0x06 F700 0x08 0 24.576 139
12.000 4 0x2 0x49 0x80 0000 0x0A 0 22.5792 120
4 0x2 0x40 0x00 0000 0x08 0 24.576 131
24.000 8 0x3 0x49 0x80 0000 0x0A 0 22.5792 120
8 0x3 0x40 0x00 0000 0x08 0 24.576 131
12.288 4 0x2 0x49 0x80 0000 0x0A 1 22.5792 118
4 0x2 0x40 0x00 0000 0x08 1 24.576 128
24.576 8 0x3 0x49 0x80 0000 0x0A 1 22.5792 118
9.600 4 0x2 0x49 0x80 0000 0x08 0 22.5792 151
4 0x2 0x50 0x00 0000 0x08 0 24.576 164
19.200 8 0x3 0x49 0x80 0000 0x08 0 22.5792 151
8 0x3 0x50 0x00 0000 0x08 0 24.576 164
13.000 4 0x2 0x45 0x79 7680 0x0A 1 22.5792 111
4 0x2 0x3C 0x7E A940 0x08 1 24.576 121
26.000 8 0x3 0x45 0x79 7680 0x0A 1 22.5792 111
8 0x3 0x3C 0x7E A940 0x08 1 24.576 121
PLL_OUT CLKOUT_DIV (2) CLKOUT_DIV (3) CLKOUT_DIV (4) CLKOUT_DIV (8)
22.5792 MHz 11.2896 MHz 7.5264 MHz 5.6448 MHz 2.8224 MHz
24.576 MHz 12.288 MHz 8.192 MHz 6.144 MHz 4.096 MHz