Cirrus Logic CS4399, Manual

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46 DS1113F1
CS4399
4.12 Control Port Operation
The control-port uses the I
2
C interface, with the chip acting as a slave device. The I
2
C control port can operate in the
following modes
:
• Standard Mode (SM), with a bit rate of up to 100 kbit/s
• Fast Mode (FM), with a bit rate of up to 400 kbit/s
• Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s
SDA is a bidirectional data line. Data is clocked into and out of the CS4399 by the SCL clock. Fig. 4-29 , Fig. 4-30 , and
Fig. 4-31 show signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while SCL
is high. A stop condition is defined as a rising transition of SDA while SCL is high. All other transitions of SDA must occur
while SCL is low.
To configure the last two bits of I 2 C address, CS4399 detects the ADR resistor connection type and measures the
resistance upon a device power up (POR event) or after a hardware reset event (RESET deasserted). Based on the
detected resistance, the I
2 C address is latched and cannot be changed until the next hardware reset event. The I 2 C
address configuration is not ready until t
PUD
after the hardware reset event. During this period, the CS4399 does not
respond to any user-issued I 2 C command. After configuration, the IC tristates the ADR pin and becomes high impedance
internally to avoid a constant bias current.
When the ADR pin is directly connected to ground, the last two bits of the I
2
C address are configured as 00 (default). For
the other options, use a resistor (with 5% accuracy) as suggested in the Table 4-12 .
If the operation is a write, the 3 bytes after the chip address are the memory address pointer (MAP) that select the address
of the register to be read or written to next. The byte following the MAP is the control byte. Bit[0] of the control byte, INCR,
selects whether autoincrementing is to be used (INCR = 1), allowing successive reads or writes of consecutive registers.
Bits[2:1] of the control byte indicate the size of the data for the autoincrement to be acted on.
Table 4-13 explains the
format for the I 2 C control byte.
Each byte transferred on the I 2 C bus is separated by an acknowledge (ACK) bit. The CS4399 acknowledges each input
byte read from the host, and the host must acknowledge each byte transmitted from the CS4399.
Table 4-12. I 2 C Address Configurations
Connection Type Resistor Value (

) Last Two Bits of I 2 C Address
Pull-up to VL 0 11
Pull-up to VL 4990 10
Pull-down to GND 4990 01
Pull-down to GND 0 00 (Default)
Table 4-13. I
2
C Control-Byte Format
Bit Name Description
7:3 — Reserved
Default: 0
2:1 SIZE Register access width. Specifies the width of the register access.
00 8-bit (1 byte)
01–11 Reserved
0 INCR Setting this bit allows the MAP address to autoincrement. The MAP address automatically increments every SIZE + 1 bytes
accessed consecutively.
0 Disabled
1 Enabled