Preprogrammed Fuses
The configuration of the processor fuses can be performed through the SPI interface with the
AVR ISP programmer or the JTAG ICE programmer and AVR Studio 4. The JTAG ICE fuse
window is depicted in figure 18 and 19. The CC2420DB is configured with the following fuses
enabled:
1. On Chip Debug Enabled
2. JTAG Interface Enabled
3. Serial program downloading (SPI) enabled
4. Preserve EEPROM memory through the Chip Erase Cycle
5. Boot Flash section size = 512 Boot start address
6. Boot vector enabled (default address = $0000)
7. Brown-out detection level at VCC 2.7 V
8. Brown-out detection enabled
9. Ext.Crystal/Resonator High Freq.; Start Up time: 16CK + 64 ms [CKSEL=1111
SUT=11]
Note:
When using the JTAG ICE mkII or the AVR ISP programmer the boot vector fuse must be
disabled.
Chipcon AS
SmartRF
®
CC2420DBK Demonstration Board Kit User Manual
(rev. 1.3) 2004-11-03 Page 31/ 52
Figure 18: AVR Studio Fuses Window CC2420DB
