18–Running User Diagnostics in DOS
Diagnostic Test Descriptions
270
83840-546-00 N
C3
CAM Access
Verifies the content-addressable memory (CAM) block by perform-
ing read, write, add, modify, and cache hit tests on the CAM asso-
ciative memory.
C4
TPAT Cracker
Verifies the packet cracking logic block (the ability to parse TCP, IP,
and UDP headers within an Ethernet frame) and the checksum or
CRC offload logic. In this test, packets are submitted to the chip as if
they were received over Ethernet and the TPAT block cracks the
frame (identifying the TCP, IP, and UDP header data structures) and
calculates the checksum or CRC. The TPAT block results are com-
pared with the values expected by Cavium 8400/3400 Series User
Diagnostics and any errors are displayed.
C5
FIO Register
The fast IO (FIO) verifies the register interface that is exposed to the
internal CPUs.
C6
NVM Access and
Reset-Corruption
Verifies non-volatile memory (NVM) accesses (both read and write)
initiated by one of the internal CPUs. It tests for appropriate access
arbitration among multiple entities (CPUs). It also checks for possi-
ble NVM corruption by issuing a chip reset while the NVM block is
servicing data.
C7
Core-Reset Integrity
Verifies that the chip performs its reset operation correctly by reset-
ting the chip multiple times, checking that the boot code and the
internal uxdiag driver loads and unloads correctly.
C8
DMA Engine
Verifies the DMA engine block by performing numerous DMA read
and write operations to various system and internal memory loca-
tions (and byte boundaries) with varying lengths (from 1 byte to over
4 KB, crossing the physical page boundary) and different data pat-
terns (incremental, fixed, and random). CRC checks are performed
to ensure data integrity. The DMA write test also verifies that DMA
writes do not corrupt the neighboring host memory.
C9
VPD
Exercises the Vital Product Data (VPD) interface using PCI configu-
ration cycles and requires a proper boot code to be programmed
into the non-volatile memory. If no VPD data is present (the VPD
NVM area is all 0s), the test first initializes the VPD data area with
nonzero data before starting the test and restores the original data
after the test completes.
C11
FIO Events
Verifies that the event bits in the CPU’s fast IO (FIO) interface are
triggering correctly when a specific chip events occur, such as a
VPD request initiated by the host, an expansion ROM request initi-
ated by the host, a timer event generated internally, toggling any
GPIO bits, or accessing NVM.
Table 18-2. Diagnostic Tests (Continued)
Test
Number
Test Name
Description
