Casio QT-6600, Service Manual

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9-4. CPU Exceptional Error
The functions of the CPU (SH series) include exception handling. If an exception other than reset and
general interrupt (hereafter called “general exception”) occurs, the OS displays a message as shown
below and stops the operation of ECR, because the operation after that cannot be guaranteed.
The example shown below indicates the screen displayed when “reservation instruction code
exception” occurs.
The values of error no., error point and access adrs vary according to errors.
CPU Exceptional Error !!
error no. 180
error point ffffd47e
access adrs 0

error no.:
Indicates the exception code of the general exception.
From this code, the operation that causes the general exception is known.

error point:
Indicates the point on the memory where the operation instruction that causes the above general
exception is located (program counter).
However, an illegal address may be displayed depending on the exception code.

access adrs:
Indicates the address that is accessed according to the operation instruction that causes the above
general exception.
However, the address is 0 (zero) and has no meaning if the access is not the cause.

Error Code Correspondence Table
error no. error point access adrs Description of error
40 Location where error occurs Logical address of comparison source TLB address comparison
results in address mismatch
60 Location where error occurs Logical address of error source TLB entry is invalid
80 Location where error occurs Logical address of error source Initial page write exception
A0 Location where error occurs Logical address of error source TLB protection exception
(read)
C0 Location where error occurs Logical address of error source TLB protection exception
(write)
E0 Location where error occurs Address of read destination CPU address error (read)
100 Location where error occurs Address of write destination CPU address error (write)
180 Location where error occurs 0 Reservation instruction code
exception
1A0 Location where error occurs 0 Slot illegal instruction
exception