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30
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
4.7
Oscillators and Clock Inputs
The oscillator and clock scheme for the
GR-CPCIS-XCKU Board
Board is shown in Figure 17. On
this board, all oscillators are soldered to the PCB, except for X3 which is an 8 pin DIL socket for a
user defined oscillator.
X1 provides a 20MHz oscillator input for the GR716 main input clock
X2 provides a 50MHzoscillator input for the GR716 Spacewire clock
Y1 is not fitted, but could be used as a Crystal for the internal GR716 oscillator.
X3 is a DIL8 socket for a user defined oscillator input to the FPGA
X4 is a 300MHz LVDS differential clock input to the FPGA. This clock is used internally by the
FPGA to generate the Clocks for the DDR3 memory interface.
X5 is a 156.25MHz LVDS differential clock input to the FPGA. This clock is used internally by the
FPGA to generate the Clocks for the GTH high speed serial transceivers.
Y2 is a 12.00 MHz crystal input for the FTDI USB/Serial interface chip
Y3 & Y4 are 25.00 MHz crystal inputs for the ETH0 and ETH1 Ethernet PHY chips respectively.
The F1_GC_CLK, F1_CLK_M2C and F1_CLK_C2M are clock interfaces routed between the FPGA
and FMC connector for possible future use, depending on the FPGA and FMC board logic
requirements.