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Kungsgatan 12 | SE-411 19 Goteborg | Sweden
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21
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
The interface signal to GR716 interface pin correspondence is listed in Table 8 .
Table 8
FTDI Interface to GR716 pin mapping
Interface
Signal
GR716 Signal
GR716 pin
UART2
TXD2
GPIO50
65
RXD2
GPIO51
66
DSU
DSUTX
DSUTX
8
DSURX
DSURX
7
4.6.5
FMC Mezzanine Board Interface
The Mezzanine connector of the
GR-CPCI-S-BM-MEZZ
is a FMC High Pin Count (400 pin - Male)
connector conforming to the VITA57.1 format. However, due to insufficient FPGA pins being
available, not all of the HPC pins are populated.
The electrical functions connected over this interface are represented in the block diagram in Figure
11.
•
LA_P[33..0]/LA_N[33..0]
34 LVDS differential pairs (configurable also as 68 single ended
1.8V LVCMOS signals). Functionality and configuration depend on the logic implemented in
the FPGA and FMC mezzanine board.
•
CLK_C2M_P/_N
LVDS differential clock from Carrier (FPGA) to Mezzanine (FMC board)
•
CLK_M2C_P/_N
LVDS differential clock from Mezzanine (FMC board) to Carrier (FPGA)
•
PRSNTN
LVCMOS18 signal, pulled high to indicate to FPGA if FMC board is installed.
•
PWRGOOD
Signal from Mezzanine board indicating the ‘Power Good’ status of the circuits
on the FMC board.
•
I2C
I2C slave signals connected from FMC board to GR716
•
DP_C2M_P/_N
High Speed serial TX pair from Carrier (FPGA) to Mezzanine (FMC)
•
DP_M2C_P/_N
High Speed serial TX pair from Mezzanine (FMC) to Carrier (FPGA)
•
GC_M2C_P/_N
Differential Clock from Mezzanine (FMC) to Carrier (FPGA)
•
JTAG
JTAG interface
•
Power
o
3V3P & 3V3PAUX 3.3V
o
VADJ 1.8V
o
+112V. As per the system requirements, this supply voltage is switched
ON/OFF under control of the FMC-ON output of the GR716.
o
VREF_A_M2C Vref output from mezzanine board to FPGA