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© Cobham Gaisler AB 

Kungsgatan 12 | SE-411 19 Goteborg | Sweden   

+46 31 7758650 | www.caes.com/gaisler 

16 

GR-CPCIS-XCKU

 

 

 

Document Data Sheet & User Manual  
Feb 2022, Version 1.2 

 
 

The interface signal to FPGA pin correspondence is listed in Table 2    .  

 

Table 2    

 

SPW Interface to FPGA pin mapping 

Interface 

Signal 

FPGA Bank 

FPGA Signal 

FPGA pin 

SPW0 

TXD_N/_P 

Bank 67 

IO_L4 

T17/T18 

 

TXS_N/_P 

Bank 67 

IO_L3 

N16/N17 

 

RXD_N/_P 

Bank 67 

IO_L2 

P16/R16 

 

RXS_N/_P 

Bank 67 

IO_L1 

P18/P19 

SPW1 

TXD_N/_P 

Bank 67 

IO_L16 

E17/F17 

 

TXS_N/_P 

Bank 67 

IO_L14 

H17/H18 

 

RXD_N/_P 

Bank 67 

IO_L21 

A19/B19 

 

RXS_N/_P 

Bank 67 

IO_L23 

A20/B20 

SPW2 

TXD_N/_P 

Bank 66 

IO_L16 

F12/F13 

 

TXS_N/_P 

Bank 66 

IO_L15 

D14/D15 

 

RXD_N/_P 

Bank 66 

IO_L13 

E15/F15 

 

RXS_N/_P 

Bank 66 

IO_L14 

F14/G15 

SPW3 

TXD_N/_P 

Bank 67 

IO_L12 

J18/K18 

 

TXS_N/_P 

Bank 67 

IO_L11 

J19/J20 

 

RXD_N/_P 

Bank 67 

IO_L9 

L18/L19 

 

RXS_N/_P 

Bank 67 

IO_L10 

J16/K16 

SPW4 

TXD_N/_P 

Bank 67 

IO_L20 

C18/D18 

 

TXS_N/_P 

Bank 67 

IO_L19 

C19/D19 

 

RXD_N/_P 

Bank 67 

IO_L13 

G19/H19 

 

RXS_N/_P 

Bank 67 

IO_L15 

F19/G20 

SPW5 

TXD_N/_P 

Bank 67 

IO_L23 

B17/C17 

 

TXS_N/_P 

Bank 67 

IO_L24 

A17/A18 

 

RXD_N/_P 

Bank 67 

IO_L17 

E20/F20 

 

RXS_N/_P 

Bank 67 

IO_L18 

E18/F18 

SPW6 

TXD_N/_P 

Bank 66 

IO_L12 

H14/J14 

 

TXS_N/_P 

Bank 66 

IO_L11 

G15/G16 

 

RXD_N/_P 

Bank 66 

IO_L10 

J15/K15 

 

RXS_N/_P 

Bank 66 

IO_L9 

K12/K13 

SPW7 

TXD_N/_P 

Bank 66 

IO_L19 

A12/A13 

 

TXS_N/_P 

Bank 66 

IO_L20 

C13/D13 

 

RXD_N/_P 

Bank 66 

IO_L18 

E12/E13 

 

RXS_N/_P 

Bank 66 

IO_L17 

D16/E16 

SPW8 

TXD_N/_P 

Bank 66 

IO_L7 

H13/J13 

 

TXS_N/_P 

Bank 66 

IO_L8 

L12/L13 

 

RXD_N/_P 

Bank 66 

IO_L5 

L15/M15 

Summary of Contents for GR-CPCIS-XCKU

Page 1: ...6 boot 256 Mbit and for data 256 Mbit The FPGA has also access to two NVM 512 Mbit SPI and Parallel Flash memory 40 bit wide FMC Mezzanine expansion connector Scrubbing interface for FPGA Available al...

Page 2: ...controller 11 4 5 Memory 13 4 6 Board Interfaces 14 4 6 1 High Speed Serial Links 14 4 6 2 Ethernet 18 4 6 3 PPS 19 4 6 4 FTDI USB Serial 20 4 6 5 FMC Mezzanine Board Interface 21 4 6 6 I2C 23 4 6 7 J...

Page 3: ...awing pdf Assembly Drawing RD3 GRMON3 User s Manual available from https www gaisler com index php products debug tools grmon3 RD4 GR716 LEON3FT Microcontroller User s Manual available at https www ga...

Page 4: ...is a 1 slot 6U high board with a CPCI S backplane format It can be used stand alone or it can be installed in a CPCI Serial rack The cutting edge Ultrascale FPGA allows the development of next generat...

Page 5: ...OIC 16 package for FPGA non volatile memory 512 Mbit SPI memory Cypress S25FL512SAGN in SOIC 16 package for GR716 boot configuration 512 Mbit SPI memory Cypress S25FL512SAGN in SOIC 16 package for GR7...

Page 6: ...Cobham Gaisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 6 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Figure 2 GR CPCIS XCKU Main Board...

Page 7: ...practices When not in use store the unit in an electrostatic protective container or bag When configuring the jumpers on the board or connecting disconnecting cables ensure that the unit is in an unp...

Page 8: ...com gaisler 8 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 4 BOARD DESIGN 4 1 Board Block Diagram Figure 3 GR CPCIS XCKU Board Block Diagram The GR CPCIS XCKU Board provides the...

Page 9: ...ard to be mounted to the board The face to face mounting distance between the main board and mezzanine boards is 10mm While the prototype board is mounted using simple 10mm nickel brass Hex spacers a...

Page 10: ...1 8V Logic banks 44 45 46 47 48 are dedicated to the 96 bit wide DDR3 Memory data interface and are powered with an I O voltage of 1 5V The pin assignment of these interfaces takes account of the ass...

Page 11: ...W Spacewire LVDS interface between GR716 and FPGA CAN3 CAN data interface between GR716 and Backplane CAN4 CAN data interface between GR716 and Backplane SPI BOOT SPI Memory interface to Serial SPI me...

Page 12: ...CLK0 GPIO14 SPI to FGPA MISO0 GPIO15 SPI to FGPA MOSI0 GPIO16 GPIO Header GPIO16 GPIO17 SPI to FGPA SLV0 GPIO18 GPIO Header GPIO18 GPIO19 GPIO Header GPIO19 GPIO20 GPIO Header GPIO20 GPIO21 GPIO Heade...

Page 13: ...peration and programming refer to RD4 4 5 Memory This boards incorporates various on board memories as represented in Figure 6 DDR3 SDRAM Dual SODIMM sockets for DDR3 SDRAM memory 96 bit wide interfac...

Page 14: ...terfaces 4 6 1 High Speed Serial Links The board incorporates a large number of SPFI and SpaceWire Links distributed between the FPGA CPCI S backplane GR716 Processor and External Front panel connecto...

Page 15: ...nks which connect to the FPGA are implemented using using the LVDS differential drivers receivers implemented in the FPGA All SPW links which connect to the backplane SPW1to SPW8 include resistors to...

Page 16: ...IO_L15 D14 D15 RXD_N _P Bank 66 IO_L13 E15 F15 RXS_N _P Bank 66 IO_L14 F14 G15 SPW3 TXD_N _P Bank 67 IO_L12 J18 K18 TXS_N _P Bank 67 IO_L11 J19 J20 RXD_N _P Bank 67 IO_L9 L18 L19 RXS_N _P Bank 67 IO_L...

Page 17: ...to FPGA pin correspondence is listed in Table 3 Table 3 SPFI Interface to FPGA pin mapping Interface Signal FPGA Bank FPGA Signal FPGA pin SPFI1 TXD1_P _N Bank 228 TX3 V6 V5 RXD1_P _N Bank 228 RX3 V2...

Page 18: ...T1 4 6 2 Ethernet A Dual Ethernet RJ45 interface is provided on the board front panel and is connected to the FPGA This interface can operate in either 100Mbit or Gbit mode and can be used for standar...

Page 19: ...L6N AU19 TXD1 Bank 64 IO_L4P AV19 TXD2 Bank 64 IO_L5P AT18 TXD3 Bank 64 IO_L6P AT19 RXD0 Bank 64 IO_L3P AU17 RXD1 Bank 64 IO_L5N AT17 RXD2 Bank 64 IO_L3N AU16 RXD3 Bank 64 IO_L7N AR17 TXCLK Bank 64 IO...

Page 20: ...al PC to interface to the following serial interfaces GR716 DSU serial interface GR716 UART 0 serial interface GR716 UART 1 serial interface FMC JTAG interface The front panel interface connector mark...

Page 21: ...onfigurable also as 68 single ended 1 8V LVCMOS signals Functionality and configuration depend on the logic implemented in the FPGA and FMC mezzanine board CLK_C2M_P _N LVDS differential clock from Ca...

Page 22: ...f the POWERGOOD signal all these signals are on the LPC section of the FMC connector The interface signal to FPGA pin correspondence is listed in Table 9 Table 9 FMC Interface to FPGA pin mapping Inte...

Page 23: ...6_P _N Bank 25 IO_L10 AT39 AU39 LA17_P _N Bank 24 IO_L13 AL30 AM30 LA18_P _N Bank 24 IO_L14 AL29 AM29 LA19_P _N Bank 24 IO_L4 AU29 AU30 LA20_P _N Bank 24 IO_L3 AW30 AW31 LA21_P _N Bank 24 IO_L6 AT29 A...

Page 24: ...Peripheral backplane slot The Slave addresses of the depend on the corresponding logic implemented Figure 12 Board I2C Interfaces 4 6 7 JTAG Two JTAG Chains are present in the designed 1 JTAG1 This J...

Page 25: ...GR ACC GR740 board could provide 2 UART 2 CAN and a Dual 1553 interface if the logic in the FPGA is appropriately configured Figure 14 FPGA GPIO interface These FPGA signals are LVCMOS18 voltage leve...

Page 26: ...35 SOCPIO12 Bank 25 IO_L3N AU34 SOCPIO13 Bank 25 IO_L4P AW35 SOCPIO14 Bank 25 IO_L2N AV34 SOCPIO15 Bank 25 IO_L1N AW34 4 6 9 Reset Circuit Two reset circuits are provided each with a TPS3705 33 proces...

Page 27: ...27 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Figure 15 Reset Circuitry 4 6 10 CPCI S Backplane The CPCI S Backplane interface is represented in Figure 16 In the standard confi...

Page 28: ...f the backplane 8 Spacewire SPW links connect from LVDS interfaces of the FPGA to the P5 P4 and P2 connectors of the backplane 2 CAN interfaces connect from the FPGAand 2 from the GR716 to the P1 conn...

Page 29: ...O_L13N AM12 RX1 Bank65 IO_L11N AN12 CAN2 TX2 Bank65 IO_L18P AK13 RX2 Bank65 IO_L14N Al13 SGPIO SDI Bank65 IO_L24N AD13 SDO Bank65 IO_L15N AJ14 SCL Bank65 IO_L15P AH14 SL Bank65 IO_T3U AE15 GA GA3 Bank...

Page 30: ...d as a Crystal for the internal GR716 oscillator X3 is a DIL8 socket for a user defined oscillator input to the FPGA X4 is a 300MHz LVDS differential clock input to the FPGA This clock is used interna...

Page 31: ...er AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 31 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Figure 17 Board level Clock Distribution Scheme G...

Page 32: ...igure 18 VCC_0V95 FPGA Vcore and BRAM supply voltages PM_3V3 Dedicated 3 3V supply for Power Monitor circuit VCC_3V3 3 3V supply for VIO for FPGA GR716 and peripherals VCC_1V8 1V8 supply for VIO for F...

Page 33: ...m Gaisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 33 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Figure 18 Power Regulation Scheme GR CPCIS...

Page 34: ...e the Cobham Gaisler GRMON3 debugging software installed on a host PC Please refer to the GRMON3 documentation for the installation of the software on the host PC Linux or Windows and for the installa...

Page 35: ...header Pull Down Install 2 3 JP7 GR716 SPIM_SCK Boot source 0 3 pin header Pull Down Install 2 3 JP8 GR716 SPIM_Sel Boot source 1 3 pin header Pull Down Install 2 3 JP9 FPGA MODE 2 0 SetsFPGA configu...

Page 36: ...rom FPGA or UART TXD from the GR716 to connector J9 pin 2 3 pin header Install 1 2 connects FPGA SOCPIO1 to HDR JP18 WD Reset Install jumper to prevent Watchdog resetting system e g during SW developm...

Page 37: ...n Header for FPGA Fan 12V J18 POWER MOLEX_0428192223_2pin Connector for 12V power input J19 SMAP1 HDR2X8pin 0 1 Header for SMAP interface J20 SMAP2 HDR2X8pin 0 1 Header for SMAP interface MEZZANINE Ta...

Page 38: ...Cobham Gaisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 38 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Figure 19 Front Panel View...

Page 39: ...5 No connect 6 TPFIN Input ve 7 TPFIC Input centre tap 8 No connect Table 1 J1a RJ45 ETHERNET Connector Table 18 J1b RJ45 ETHERNET Connector Pin Name Comment 1 TPFOP Output ve 2 TPFON Output ve 3 TPFI...

Page 40: ...aisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 40 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Table 20 J3 USB Micro connector FTDI Quad Ser...

Page 41: ...used 5 DGND Ground Table 21 J4 PPS 0 Input Pin Name Comment INNER IN Inner Pin Pulse Per Second 3V3 logic OUTER DGND Outer Pin Return Table 22 J5 PPS 1 Input Pin Name Comment INNER IN Inner Pin Pulse...

Page 42: ...m Gaisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 42 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Table 24 J7 SPW 0 interface connections to...

Page 43: ...Data Out ve Table 25 J7 SPW 1 interface connections to FPGA Pin Name Comment 1 DIN0 Data In ve 6 DIN0 Data In ve 2 SIN1 Strobe In ve 7 SIN1 Strobe In ve 3 SHIELD Inner Shield 8 SOUT1 Strobe Out ve 4...

Page 44: ...N GPIO9 1 2 GPIO10 GPIO11 3 4 GPIO12 GPIO16 5 6 GPIO1 GPIO19 7 8 GPIO20 GPIO21 9 10 GPIO22 GPIO23 11 12 GPIO24 GPIO39 13 14 GPIO40 GPIO43 15 16 GPIO44 VCC_3V3 17 18 VCC_3V3 DGND 19 20 DGND Table 28 J1...

Page 45: ...sler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 45 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Table 29 J12 DDR3 204pin SODIMM DDR3 Interface...

Page 46: ...ler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 46 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Table 30 J13 DDR3 204pin SODIMM DDR3 Interface B...

Page 47: ...Version 1 2 Table 31 J14 FPGA JTAG Connector FUNCTION CONNECTOR PIN FUNCTION DGND 1 2 VCC_3V3 DGND 3 4 TMS DGND 5 6 TCK DGND 7 8 TDO DGND 9 10 TDI DGND 11 12 nc DGND 13 14 nc Table 32 J15 PMBUS Progr...

Page 48: ...aisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 48 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Table 33 J16 FMC Mezzanine Connector extract...

Page 49: ...ower Connector Pin Name Comment 1 DGND Ground 2 VIN Power Input 12V typically TBD A Table 36 J19 SMAP 1 Header FUNCTION CONNECTOR PIN FUNCTION DGND 1 2 SMAP_INITN DGND 3 4 SMAP_DONE DGND 5 6 SMAP_PROG...

Page 50: ...mm Pull up 1 2 Pull down 2 3 JP8 GR716 SEL 3 pin header 2mm Pull up 1 2 Pull down 2 3 JP9 FPGA MODE 2x3 pin header 2mm Install Pull up Open pull down JP10 SMAP 2x4 pin header 2mm 1 2 SMAP to GR716 2 3...

Page 51: ...2MHz 12 MHz crystal soldered for FTDI interface Y3 ETH0 25MHz 25 MHz crystal soldered for ETH0 PHY Y4 ETH1 25MHz 25 MHz crystal soldered for ETH1 PHY Table 40 List of Switches Name Function Descriptio...

Page 52: ...12V from backplane switched on to on board circuits D6 ETH_1V2_PG ETH_1V2 regulator Power Good signal D7 GTH_1V8_PG GTH_1V8 regulator Power Good signal D8 1V5PG 1V5 regulator Power Good signal D9 VFMC...

Page 53: ...aisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 53 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Figure 20 GR CPCIS XCKU PCB Top View extract...

Page 54: ...isler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 54 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 Figure 21 GR CPCIS XCKU PCB Bottom View extrac...

Page 55: ...m gaisler 55 GR CPCIS XCKU Document Data Sheet User Manual Feb 2022 Version 1 2 REVISION INFORMATION Issue Date Section Page Description 1 0 2022 01 26 All New document 1 1 2022 02 08 All Updated with...

Page 56: ...ify that the information in this document is current before using this product The company does not assume any responsibility or liability arising out of the application or use of any product or servi...

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