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GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Figure 16
CPCI-S Interface
8 High-Speed Serial Links (HSSL) connect from the GTH transceiver interfaces of the FPGA to the
P6 connector of the backplane.
8 Spacewire (SPW) links connect from LVDS interfaces of the FPGA to the P5, P4 and P2 connectors
of the backplane.
2 CAN interfaces connect from the FPGA and 2 from the GR716 to the P1 connector of the backplane.
+12V power and a PSON# control signal are provided by the P1 connector of the backplane.
The interface signal to FPGA pin correspondence is listed in Table 11 .
The interface signal to GR716 pin correspondence is listed in Table 12 .
Table 11
Backplane Interface to FPGA pin mapping