PC Elite Reference
Technical Details
Figure 3-4. Write Register Bits.
___________________________
REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
___
_____ _____ _____ _____ _____ _____ _____ _____
0
BO7
BO6
BO5
BO4
BO3
BO2
BO1
BO0
1
CPT
APT
DET
END
DEC
ERR
DO
DI
2
0
SRQI
DMAO
DMAI
CO
LOKC
REMC
ADSC
3
S8
rsv
S6
S5
S4
S3
S2
S1
4
ton
lon
TRM1
TRM0
0
0
ADM1
ADM0
5
CTN2
CTN1
CTN0
COM4
COM3
COM2
COM1
COM0
6
ARS
DT
DL
AD5
AD4
AD3
AD2
AD1
7
EC7
EC6
EC5
EC4
EC3
EC2
EC1
EC0.
It is recommended that you do NOT attempt to handshake
data into and out from the IEEE bus using your own software
routines as the IEEE bus structure is complicated and the NEC
7210 chip is not trivial to control.
Interrupt Selection.
_________________
The PC ELITE card can produce interrupts for one of 13
reasons and its INT line can be connected to one of the PC
Interrupt Request lines by placing the jumper on the IRQ block
in the correct place.
In PC2a mode, the IRQ hardware is designed so that the ELITE
board will continue to generate irq requests until the source of
the interrupt is cleared. This allows for interrupt line sharing.
The interrupts are cleared by writing to 02FX where X=2-7
corresponding to the interrupt selected by the jumper on the
board. The position of the jumper MUST match the IRQ level
set in the software and the IRQ acknowledge address set on
DIPs 4-6.
In PC2 mode, there is no interrupt sharing and the IRQ
regeneration and clear logic is disabled.
To enable an interrupt the appropriate bit must be set in
the TLC interrupt mask register, write regs 1-2.
3-28
Chapter 3
