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REF: BB_SRM_xM
BeagleBoard-xM System
Reference Manual
Revision C2
Page 92 of 163
of operation. If desired, the resistors can be installed to pull the signals high. However, it
is not expected that any of the resistors will need to be installed. The DK1-DK3 pins
adjust the timing of the clock as it relates to the data signals.
7.17.5.6
MSEN
The
MSEN
signal, when low, indicates that there is a powered monitor plugged into the
DVI-D connector. This signal is not connected to the processor and is provided as a test
point only.
7.17.5.7
VREF
The
VREF
signal sets the voltage level of the
DATA
,
VSYNC
,
HSYNC
,
DE
, and
IDCK+
leads from the processor. As the processor is 1.8V, the level is set to .9V by
R64
and
R65
.
7.17.5.8
PD
The
PD
signal originates from the processor
on the
GPIO_170
pin. Because the
P
D
signal on the
TFP410
is 3.3V referenced, this signal must be converted to
3.3V
. This is
done by
U4
,
SN74LVC2G07
, a non-inverting open drain buffer. If the
GPIO_170
pin is
HI, then the open drain signal is inactive, causing the signal to be pulled HI by
R98
.
When
GPIO_170
is taken low, the output of
U4
will also go LO, placing the
TFP410
in
the power down mode. Even though
U4
is running at 1.8V to match the processor, the
output will support being pulled up to
3.3V
. On power up, the TFP410 is disabled by
R109
, a 10K resistor. When the processor powers on, pin
J25
comes in the safe mode,
meaning it is not being driven.
R109
insures that the signal is pulled LO, putting the
TFP410 in the power down mode.
7.17.5.9
TFADJ
The
TFADJ
signal controls the amplitude of the DVI output voltage swing, determined
by the value of
R95
.
7.17.5.10
RSVD2
This unused pin is terminated to ground as directed by the TFP410 data manual.
7.17.5.11
NC
This unused pin is pulled HI as directed by the TFP410 data manual.
7.17.6
DVI-D Connector
Summary of Contents for XM C2
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