BeagleBoard XM C2, Reference Manual

Page: 59 / 163

REF: BB_SRM_xM
BeagleBoard-xM System
Reference Manual
Revision C2
Page 59 of 163
0.6 V and 1.45 V and is used to power the processor core. VDD2 differs from VDD1 in
its current load capabilities with an output current rating of 600 mA in active mode.
The
VDD2 provides different voltage regulation schemes. When VDD2 is controlled by
the VMODE2 signal or with the SmartReflex interface, the range of output voltage is 0.6
V to 1.45 V. The use of the VMODE2 signal and the VDD2_VMODE_CFG,
VDD2_STEP, VDD2_FLOOR, and VDD2_ROOF registers is similar to the use of the
corresponding signals and registers for
VDD1 . VDD2 shares the same SmartReflex I2C
bus to provide voltage regulation. The VDD2_SR_CONTROL register is provided for
controlling the
VDD2 output voltage in SmartReflex mode.
When the
VDD2 is used in software-control mode, the VSEL (VDD2_
DEDICATED[4:0]) field can be programmed to provide output voltages of between 0.6
V and 1.45 V. The output voltage for a given value of the VSEL field is given by
VSEL*12.5 mV + 600 mV. If the VSEL field is programmed so that the output voltage
computes to more than 1.45 V, the TPS65950 sets the
VDD2 output voltage to 1.5 V.
7.8 Peripheral Voltages
There are 10 additional voltages used by the system that are generated by the
TPS65950 .
These are:
o
VDD_PLL2
o
VDD_PLL1
o
VDAC_1V8
o
VDD_SIM
o
VMMC2
o
VDD_VMMC1
o
CAM_2V8
o
CAM_1V8
o
USB_1V8
o
EXP_VDD
Figure 27 shows the peripheral voltages supplied by the TPS65950 .
7.8.1 VDD_PLL2
This programmable LDO is used to power the processor PLL circuitry. The
VPLL2 LDO
can be configured through the I2C interface to provide output voltage levels of 1.0 V, 1.2
V, 1.3 V, or 1.8 V, based on the value of the VSEL field (VPLLI_DEDICATED[3:0]).
On the board this rail is used to power DVI output for pins DSS_DATA(0:5),
DSS_DATA(10:15) and DSS_DATA(22:23). The VPLL2 must be set to 1.8V for proper
operation of the
DVI-D interface.