BeagleBoard XM C2, Reference Manual

Page: 90 / 163

REF: BB_SRM_xM
BeagleBoard-xM System
Reference Manual
Revision C2
Page 90 of 163
resistor packs on the BeagleBoard. The maximum clock frequency of these signals is
65MHz.
It should be noted that on the Rev A2 version, the ability to shut off the DVI-D display is
not supported. This will be fixed on the next letter revision of the board.
7.17.2 LCD Power
In order for the DSS outputs to operate correctly out of the processor, two voltage rails
must be active,
VIO_1V8 and VDD_PLL2 . Both of these rails are controlled by the
TPS65950 and must be set to 1.8V. By default, VDD_PLL2 is not turned and must be
activated by SW. Otherwise some of the bits will not have power supplied to them.
7.17.3 TFP410 Power
Power to the TFP410 is supplied from the 3.3V regulator in
U1 , the TPS2141 . In order to
insure a noise free signal, there are three inductors, L4 , L5 , and L6 that are used to filter
the 3.3V rail into the TFP410.
7.17.4 TFP410 Framer
The
TFP410 provides a universal interface to allow a glue-less connection to provide the
DVI-D digital interface to drive external LCD panels. The adjustable 1.1-V to 1.8-V
digital interface provides a low-EMI, high-speed bus that connects seamlessly with the
1.8V and 24-bit interface output by the processor. The DVI interface on the BeagleBoard
supports flat panel display resolutions up to XGA at 65 MHz in 24-bit true color pixel
format.
Table 15 is a description of all of the interface and control pins on the TFP410 and how
they are used on BeagleBoard.
Table 15. TFP410 Interface Signals
Signal Name Description Type Ball
DATA[23:12] The upper 12 bits of the 24-bit pixel bus. I 36–47
DATA[11:0] The bottom 12 bits of the 24-bit pixel bus. I 50–55.56-
53
IDCK+ Single ended clock input. I 57
IDCK- Tied to ground to support the single ended mode. I 56
DE Data enable. During active video (DE = high), the transmitter
encodes pixel data, DATA[23:0]. During the blanking interval
(DE = low), the transmitter encodes HSYNC and VSYNC.
I 2
HSYNC Horizontal sync input I 4
VSYNC Vertical sync input I 5
DK3 These three inputs are the de-skew inputs DK[3:1], used to
adjust the setup and hold times of the pixel data inputs
DATA[23:0], relative to the clock input IDCK±. I 6
DK2 I 7
DK1 I 8
A low level indicates a powered on receiver is detected at the