BeagleBoard XM C2, Reference Manual

Page: 58 / 163

REF: BB_SRM_xM
BeagleBoard-xM System
Reference Manual
Revision C2
Page 58 of 163
7.7.5 Main Core Voltages Smart Reflex
VDD1 and VDD2 regulators on the TPS65950 provide SmartReflex-compliant voltage
management. The SmartReflex controller in the processor interfaces with the TPS65950
counterpart through the use of a dedicated I2C bus. The processor computes the required
voltage and informs the TPS65950 using the SmartReflex I2C interface.
SmartReflex control of the
VDD1 and VDD 2 regulators can be enabled by setting the
SMARTREFLEX_ENABLE bit (DCDC_GLOBAL_CFG[3]) to 1. To perform VDD1
voltage control through the SmartReflex interface, the TPS65950 provides the
VDD1_SR_CONTROL register. The MODE field of the VDD1_SR_CONTROL register
can be set to 0 to put VDD1 in an ACTIVE state; setting the field to 1 moves
VDD1 to a
SLEEP state. VDD1 output voltage can be programmed by setting the VSEL field of the
VDD1_SR_ CONTROL register. The VDD1 output voltage is given by VSEL*12.5 mV
+ 600 mV.
7.7.6 VDD1
The
VDD1 rail is supplied by the VDD1 regulator of the TPS65950 . The VDD1
regulator is a 1.1A stepdown power converter with configurable output voltage between
0.6 V and 1.45 V in steps of 12.5 mV. This regulator is used to power the processor core.
The processor can request the
TPS65950 to scale the VDD1 output voltage to reduce
power consumption. The default output voltage at power-up depends on the boot mode
settings, which in the case of the BeagleBoard is 1.2V. The output voltage of the
VDD1
regulator can be scaled by software or hardware by setting the ENABLE_VMODE bit
(VDD1_VMODE_CFG[0]). In each of these modes, the output voltage ramp can be
single-step or multiple-step, depending on the value of the STEP_REG field of the
VDD1_STEP[4:0] register. The VOCORE_1V3 rail should be set to 1.3V after boot up.
Apart from these modes, the
VDD1 output voltage can also be controlled by the
processor through the SmartReflex I2C interface between the DM3730 and the
TPS65950 . The default voltage scaling method selected at reset is a software-controlled
mode. Regardless of the mode used, VDD1 can be configured to the same output voltage
in sleep mode as in active mode by programming the DCDC_SLP bit of the
VDD1_VMODE_CFG[2] register to 0. When the DCDC_SLP bit is 1, the sleep mode
output voltage of
VDD1 equals the floor voltage that corresponds to the VFLOOR field
(VDD1_VFLOOR[6:0]).
7.7.7 VDD2
The
VDD2 voltage rail is generated by the TPS65950 using the VDD2 regulator. The
VDD2 regulator is a stepdown converter with a configurable output voltage of between