Barco SLM R12 Plus, Service Manual, Page: 75 / 281

11. Signal Input Selection R763850 & R763851
Image 11-3
Block diagram AD9888
Output of the ADC is an RGB 48 bit digital signal. Each color is 2x8bit (odd and even). The split in odd and even is done to lower
the clock (clock is half by the odd/even split).
11.3.1.2.4 DVI Output (see sheet 3/11).
Description
The SIL 160 uses Panellink technology to support displays ranging from VGA to UXGA (25 to 165MHz). The BUS_TX signal can be
either the DVI IN signal that has been re-synced, or, the processed analog input ([Active Image] in the Input Slot Selection menu).
Note that an analog RGB signal, that has been processed by the PMP has undergone some delay. The DVI OUT signal is not
synchronized with the input signal and with the image shown on the projector. It is advised then to install a minimum delay in the"
advanced settings" in the "installation menu" (see owner’s manual).
11.3.1.2.5 Data multiplexing (see sheet 7- 8/11)
Description
We have four 48-bit digital signals:
• 48 bit from the fixed input selector 1
• 48 bit from the fixed input selector 2
• 48 bit from the optional digital input 1
• 48 bit from the optional digital input 2
The multiplexing of the four 48 bit RGB signals is done by two FPGA’s: I23 for the odd pixels and I24 for the even pixels.
The two FPGA’s have almost the same programming done by a third FPGA I25.
One of the four input channels is clocked to the output channel 1(XI1) depending on the level of the signals SLOTSEL0_XI1 and
SLOTSEL1_XI1. The same story goes for the second output channel XI2 depending on SLOTSEL0_XI2 and SLOTSEL1_XI2.
For Picture in Picture (PIP) applications, there are two full outputs to the PMP. The latter is also designed to accept and process
simultaneously two signals
11.3.1.2.6 Sync switching and control, I25 (sheet 9/11)
Description
The input boards are controlled by the third FPGA (I25). The FPGA is programmed by the projector’s microcontroller at start up.
The FPGA controller I25 performs following tasks:
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