Technical data
40
Panel PC 2200 built-in devices User's manual V 1.05 Translation of the original documentation
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PCIe 2
Power down
IF option 2x POWERLINK/nvSRAM
POWERLINK
Green
Green/Red
LED L2
LED L3
POWERLINK
nvSRAM
Green
LED L1
FPGA
Figure 13: 2x POWERLINK / nvSRAM IF option (5ACCIF01.FPLK-000) - Block diagram
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PCIe 2
Power down
IF option POWERLINK/RS232/FRAM
POWERLINK
RS232
Connector,
10-pin
F_I0
Green
Green/Red
LED L2
LED L3
FRAM
FPGA
Figure 14: POWERLINK / RS232 / FRAM IF option (5ACCIF01.FPLS-000) - Block diagram
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PCIe 2
Power down
IF option POWERLINK/RS232/nvSRAM
POWERLINK
RS232
Connector,
10-pin
F_I0
Green
Green/Red
LED L2
LED L3
nvSRAM
FPGA
Figure 15: POWERLINK / RS232 / nvSRAM IF option (5ACCIF01.FPLS-001) - Block diagram
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PCIe 2
Power down
IF option POWERLINK/RS232/CAN/FRAM
POWERLINK
RS232
CAN
Connector,
10-pin
Yellow
Green
Green/Red
LED L1
LED L2
LED L3
Terminating
resistor
FRAM
FPGA
Figure 16: POWERLINK / RS232 / CAN / FRAM IF option (5ACCIF01.FPSC-000) - Block diagram
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PCIe 2
Power down
IF option POWERLINK/RS232/CAN/X2X/nvSRAM
POWERLINK
RS232
Connector,
10-pin
Yellow
Green
Green/Red
LED L1
LED L2
LED L3
Terminating
resistor
nvSRAM
CAN
X2X
Insulator
Insulator
FPGA
Figure 17: POWERLINK / RS232 / CAN / X2X / nvSRAM IF option (5ACCIF01.FPSC-001) - Block diagram